10-11-2016 02:16 PM
What about IIR filter which work perfectly ! how can i use it in FPGA i'am looking for solution here ! if you understand what do you sugess !!
10-12-2016 10:24 AM
Someone from NI may need to join in on this message thread and comment. I looked at that Express VI. Interesting thing is that I can't do Altenbach's recommendation of looking into the Express VI. It seems to have a different shortcut menu than other Express VI's and I can't do an Open Front Panel to turn it into regular LabVIEW Vi's to poke around in.
I think he has a point about the scaling factor between those numbers. I tried entering 50 mHz in the Express VI and saw that the sample graph went empty. I decreased the sampling rate to 5 KHz.and the line came back. Than decreased the filter to 5 mHz and it went away again. It seems that the ratio of sampling rate to frequence has to be about 145,000:1 or smaller (based on a few data points I checked) for the line to show up in the Express VI. Probably a limitation built into the express vi so that it can work on the FPGA.
10-12-2016 12:52 PM
OK, I have to ask, your frequency band is 2 milliHertz to 10 milliHertz. Is this correct milli (10^-3)? Or do you mean MegaHertz (10^6) or kilo (10^3).
You won't be able to sample much at mHz freqs but MHz is more realistic physical value.
Rich J
10-12-2016 03:19 PM
mHz means (10e-3) physicaly i want to have big constant filter Taux.
10-13-2016 09:28 AM
Tau - time constant. T=RC=1/2pi*fc = at 50mHz makes tau a big big number. OK.
10-13-2016 12:02 PM
No Sorry . is not enough for my physicaly system.
i wana to have Tau=10s;50s;150s
10-13-2016 12:08 PM
Then you will need to lower your sampling rate.
At 1 kHz, 150 seconds is 150,000 samples. That seems like a lot of data for an FPGA to handle.
10-14-2016 07:17 AM - edited 10-14-2016 07:18 AM
someone can explain Why when i put
cutooffrequency = 50mHz
sample rate = 50k S/s physicaly i obtain Cutoff frequency = 0.11Hz !!!!!!!! when i wana to lower physically cutof frequency what should i do ?!!!
i don't understand anything with butterworth filtre configuration. thanks for help.
10-17-2016 06:00 PM
I think some of the early comments about posting your code would be good! Let us take a crack at it!
-Bear
10-18-2016 03:17 AM
the code its very simple, its enough to use filtre butterworth bloc in the "FPGA math" library of labview. with PXI7841R. the code contain 2 loops :
1**the First loop (loopSCTL) to generate square signal.
2** the second its to do the task of filtration and see the filtred signal.
as its mentionned in the figure linked here.