Bundle FPGA Reference Bug

[GregFreeman]

I went to this link here and followed the steps, thinking it may resolve my issue because my issue is somewhat similar. Except, I am trying to bundle my reference rather than pass it to a subVI. After it is bundled, I get a refnum of 0. See the attached probe values.

I have to assume someone here has bundled an FPGA reference before. How did you work around this? I am using LabVIEW 2009. Hopefully the screenshot is enough, I can't post the code publicly.

Thanks in advance.

I should add, my main cluster is a type def cluster, and the FPGA VI Ref 2 is a strict type def control its self, inside my type def main cluster. Also, there is no error coming out of the run FPGA invoke node.

[GregFreeman]

BUMP

[nathand]

Have you tried probing the wire on each side of the FPGA Invoke Node, especially the wire that goes into the bundle?  I note from your screenshot that the TCP Conn Ref is also 0 in the probe, which makes me wonder if you're getting an error from the FPGA Run.

[GregFreeman]

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@nathand wrote:

Have you tried probing the wire on each side of the FPGA Invoke Node, especially the wire that goes into the bundle?  I note from your screenshot that the TCP Conn Ref is also 0 in the probe, which makes me wonder if you're getting an error from the FPGA Run.

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"Also, there is no error coming out of the run FPGA invoke node."

I have gotten rid of bundling and just pass the reference directly and the code works fine. I only have problems when it is bundled, so the issue is definitely in the bundling.

[Greg_J]

Does the probe only show 0 when you probe the cluster (at 40 in your picture)?  What does the probe show if you place it on the reference itself between the Run Invoke Node and the Bundle By Name?

- Greg J

[GregFreeman]

It is still a valid refnum after the run method. I changed my code and just wire the refnum directly to invoke methods and into subVIs where needed and all the code works. Control values are set correctly in FPGA and my code runs fine. It seems to just be lost when I bundle it. The cluster is simply serving to avoid wire clutter so it's not a big deal, but it definitely seems like a bug.

[Greg_J]

Have you probed the output of the unbundle function to see if the FPGA VI Reference itself is corrupt or if it's just the probe window?  I was able to reproduce this, however I noticed that when probing the output of the unbundle function all reference integers appeared to be as the were before being bundled.  I filed CAR # 252446 on the behavior that I saw, but please let us know if you are seeing anything different.

Thanks!

- Greg J