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Buffering 10 AI on sbRIO

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Hi,

I am using the FPGA wizard to buffer 10 analog inputs for a single board RIO. I need the loop rate to be at least 15 kHz in order to identify a 7 kHz square wave input. I can usually get the signal to buffer fine until I try to do any sort of data manipulation, then I have overflow problems and have to increase the sample size (which usually is too slow to be as responsive as I would like). Is there a way to bypass this problem? Would using shared variables help? Multiple VI's?

 

Thanks!

 

--Eli

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Hey Eli,

 

When you mean buffers do you mean the DMA FIFOs? Dont forget that it is a double buffer.  The size you set in the project is for the FPGA size but you can increase the size on the RT OS using the configure method which will give you a bit more of a buffer.

 

If not another thing you can try is increase the amount of data you read at a time, this is typically more efficient.

 

If neither of these help then you will probably have to take a look at the efficiency of your processing, does it execute in less time that it takes to acquire the data it uses?  Buffers only account for jitter, if your processing fundamentally takes longer than the data acquisition no amount of buffer will save you, just put of the inevitable.

 

Cheers,

James Mc
========
CLA and cRIO Fanatic
My writings on LabVIEW Development are at devs.wiresmithtech.com
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Hi James-

 

Thanks so much for responding.

 

I amusing the FPGA wizard to set up my FIFO buffer. I think you are right that my processing takes longer than the data acquisition, which would explain the slowing down and overflow warnings.

 

I am using the inputs to extract a frequency from a squarewave and determine whether it is 500 Hz or 7000 Hz. Do you have suggestions as to what would be a faster method? Would the built-in FPGA filters be a good idea?

 

Thanks!

--Eli

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Solution
Accepted by EliKuhlmann

if you are only measuring the frequency of the signal using analog inputs, i would process the data right on the FPGA.  the rates that you are describing should not be a problem for FPGA.  look to your algorithm first.

Stu
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Hey Eli,

 

I would double Stu's point.  It should be relatively simple to measure the period and therefore the frequency of the squarewave on the FPGA.  This way that does all the hard work so your RT CPU doesn't have to (you wouldn't even need DMA FIFOs then). I have found one example at http://zone.ni.com/devzone/cda/epd/p/id/5835 but I think there is probably simpler ways out there as well.

 

If this isn't an option for any reason then I think even on RT you could probably just find the rising edge locations in the data and measure the time between them, the FFT is quite an intensive way of doing this.  At the very least ensure that your data length into the FFT is a power of 2 (e.g. 1024 or 2048 samples) as this allows the algorithm to use the most efficient version of the transform.

 

Cheers,

James Mc
========
CLA and cRIO Fanatic
My writings on LabVIEW Development are at devs.wiresmithtech.com
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