Bit packing and unpacking

[PeterGrant]

Hello there,

I'm trying to create some logic for sending N number of channels through a DMA FIFO. What I'm trying to solve this moment is how to add some info in front of the measured data.

Using a 32bit word, I want the first 3 bits to represent the module number. The next 4 the channel number, and then the final 25 bits the data. 

The problem I'm facing is how to decode that information. I've got it working with a 64bit word, split into 16/16/32, however, I don't want to use 16bit words for the module number and channel number.

Do you have any suggestions on how I should be decoding my 32bit word?

Thanks,

Peter 

[wiebe@CARYA · Accepted solution]

If you need 3 bits, lets say bit 7, 8 and 9, rotate (or shift) 7 to the right. Bits 7, 8 and 9 are now bit 0, 1 and 2. AND this with 7 ( 111 binary) and you have your result.

[wiebe@CARYA]

As an alternative, you can convert the number to a Boolean array (Number To Boolean Array function). Then, you can pick your Booleans and put them in an array, and convert back with Boolean Array To Number.

I think this solution should not be preferred, but you'll see it a lot. I don't like using arrays, especially on FPGA. Not sure if this dislike is justified, but I stick to normal bit manipulation if I can avoid arrays.

[GerdW]

Hi Peter,

start like this:

Using AND to limit number of used bits, using Rotate to shift bits, using OR to stuff bits into one longword…

[PeterGrant]

Missed the use of the AND. Thanks for the help!

[billko]

I usually use a cluster of Booleans instead of an array.  The cluster structure makes sure all bits are always represented.  Then you just bundle the bits you want to change.  I don't do this for efficiency; rather, I do it because it most visually represents what is being done with no ambiguity whatsoever.  (As an added bonus, you can name each Boolean if you want to match the Booleans to signal names and such, furthering the "self-documentation" effort.)

[wiebe@CARYA]

---

@billko wrote:

I usually use a cluster of Booleans instead of an array. 

---

So how do you get from a number to a cluster? Or do you use number to Boolean array and then array to cluster? Especially on an FPGA I'd avoid clusters and arrays (again, no idea if this is grounded). On a PC it isn't a bad idea.

[rolfk]

---

wiebe@CARYA wrote:

I think this solution should not be preferred, but you'll see it a lot. I don't like using arrays, especially on FPGA. Not sure if this dislike is justified, but I stick to normal bit manipulation if I can avoid arrays.

---

Arrays of booleans are definitely suboptimal even on other platforms than FPGA. There is a small chance that the FPGA platform does some specific optimization under the hood to convert boolean arrays of limited size into integers anyways as that is more efficient to implement into hardware but on non-FPGA platforms each boolean always uses up an entire byte and so an array of 32 booleans uses 32 bytes, needs to be dynamically allocated and deallocated and incurs extra overhead when referencing the bits. If you use integers with boolean arithmetic instead you keep the code the same on all LabVIEW platforms and also get the most performant solution on each platform too!

[wiebe@CARYA]

@Rolfk:

Thanks. I'm not sure if it's intuition or that I actually benchmarked it years ago.

Of course, if you're going to do a lot of this (bit-packing\unpacking), it makes sense to make a small set of VI's to do this. By making the VI's inlined, performance should be high.

[crossrulz]

---

@billko wrote:

I do it because it most visually represents what is being done with no ambiguity whatsoever.

---

When I am doing this bit packing, I tend to have my numerics displayed in hex and/or binary and show all of the preceding zeros as well.  For example, an U32 I will use %08x for the format.  This QuickDrop shortcut helps a lot: Format Numeric.vi.  And also make sure the radix is visible when you do this (I have not had the time yet to add that to my plugin).