Best way to transfer data between loops in FPGA VIs

[Zouhair]

Hi,

I'm using a FlexRio Board PXIe 7962, with an I/O module 5781.

I've set the Top level Clock to 80MHz (Base Clk 40M), and I'm implementing two loops in the FPGa VI: In the first one, I'm using a SCTL (20M) where I'm getting Digitized Data (1.5MHz) from the NI 5781, then multiplying it by a DDS Signal (1.8MHz), then I'm filtering (band-pass around 300kHz)) the product.

My question is: If what I've implemented is correct, what is the best way to transfer the first loop data running at 20MHz, to the second one running at 1MHz ? (without loosing Data of course since the signal interest is at 300kHz)

and similarly : what is the best way to transfer the second loop data running at 1MHz, to a Host VI ? DMA FIFOs?

Thank you in advance,

Zouhair

[crossrulz]

Your top loop is not running at 20MHz.  Only what is inside of the SCTL will run in a single 20MHz clock cycle.  So your filters are not in 20MHz clock rate.

And I'm not even seeing a reason for your bottom loop.  Why not just use the DMA to send the data directly to the host in your top loop?

[Zouhair]

I've set the loop timer in the first frame to 4 clock ticks of 80MHz, so I imagine that what follows should not work under 20MHz, Am I mistaken?
About the bottom loop, there will be some processing blocks in it later, but I wanted to check it's input signal first before implementing (spectral and temporel views with a bandwidth of 1M rather than 20M)
Thanks.

[crossrulz]

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@Zouhair wrote:
I've set the loop timer in the first frame to 4 clock ticks of 80MHz, so I imagine that what follows should not work under 20MHz, Am I mistaken?

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Yes you are.  That SCTL will execute in the 20MHz clock time.  Everything else in the loop is just adding to that time.

[Zouhair]

So how can I make the filters work at 20MHz? Knowing that they can't be put in an SCTL as you know.

[David-A]

Hello Zouhair,

The while loop will always be running in the Top Level clock domain, which is by default 40 MHz, and then inside of that you have a single cycle timed loop (SCTL) running at 20MHz. This is wonky for a lot of reasons, but for starters the analog input node from the 5781 must be in the IO Mod Clock 0 clock domain or else you get glitched data. The getting started examples in the example finder demonstrate this. I would recommend starting from those.

And I highly recommend browsing The NI LabVIEW High-Performance FPGA Developer's Guide. You would want to read the section titled HIGH-PERFORMANCE PROGRAMMING WITH THE SINGLE-CYCLE TIMED LOOP which will help describe why the code you currently have doesn't work quite like you think it is. And then the DATA TRANSFER MECHANISMS  section has information on how to transfer data between loops. It even has a handy table on page 81.

[Zouhair]

Hello,

I will take a look at what you recommended.
the reason why I am putting an SCTL in the while loop is because I don't think the processing ( DDS generation + Multiplication + Filtering) could take one clock cycle of the 40 MHz, that's why I've chosen a derived clck to be my top level clock (80MHz) and a processing at 20MHz, this way I have 80/20 =4 clock ticks to perform the data treatment. Besides, I have some performance problems (confirmed by one of your colleagues) with Labview FPGA filters when I use a higher sample rate/ cutoff frequency.

[David-A]

Unless you are providing the 5781 an external sample clock, the ADC on the 5781 will default to using the 100MHz on boad oscillator to generate 100MS/s. Whether sourced externally or from on board, the clock the ADC uses to sample is also exported to LVFPGA in the form of IOModClock0. You are required to place the AI node in a clock domain driven by IOModClock0 which means you will always be generating 100MS/s of data using the default settings.

If you need to generate a lower sampling rate for filtering purposes you can try putting only 1/10 samples into a fifo and pulling those samples out of a fifo in whichever loop you want to do the processing. Or rather than throwing away 9/10 samples you could try using the Rational Resampler.vi. However you decide to decimate your data, just make sure that you are consuming the data faster than you are producing it.