Array of Cluster slow but faster when surrounded with a sequence structure (optimization)?

[Foreshadow20]

Hi,

I'm unable to explain or figure out what is going with the following code (screenshot only).

I was trying to find the cause of the case "Get TC" taking 150ms. So I added some structures in order to calculate the time and once the structure surrounded the unbundle of TC, the execution time dropped to near 1ms. I would have assumed that it would take more time as it adds "copies of data".

Is LabVIEW somehow detecting that no change occurred from the previous data copy to the structure? (I'm using LabVIEW 2011)

TC is an array of small cluster of 6 strings. The Array is about 9000 elements.

TC array is fixed at that point in the code and doesn't change.

TC is the largest memory allocation of the lower shift register

[pauldavey]

How did you wire it up for testing the execution time?  How you wire a sequence structure can impact on what you measure as the execution time.

[altenbach]

A structure is a synchronization boundary. There is no data copy.

I don't see anywhere how you measure the timing.

Please attach your actual VI. There is no way to troubleshoot that from a picture.Was the VI just up-converted to a new version?

[Foreshadow20]

On that screen shot I only kept the "Clock" (Tick Count) and the "Clock Delta" (Tick Count difference) for each while loop iteration and the probe on the Error Line. Both are enough to show the delay through the "Loop" indicator and the refresh rate of the probe.

I originally also had a "Clock" before the sequence and "Delta" after the sequence, which is how I determined the speed up from the sequence. Maybe I can video the code running in both cases. I cannot upload the code as there's too much Intellectual Property involved.

[Foreshadow20]

(Odd that my reply didn't work)

The "Clock" and "Delta Clock" on the Error Line with the "Loop" indicator gives the time for the While Loop Iteration and the refresh rate of the probe is another sign of the slowdown from the case. I also had a conditional probe that would halt the iteration if the delta time was greater than 50ms.

Note: I cannot add the code as it contains too much Intellectual Property. I can video snapshot the difference.

[altenbach]

You also have a probe after the +1, that will probably slow you down. Have you tried with debugging disabled?

[Foreshadow20]

The probe didn't slow the loop down by 150ms. When the sequence structure is up it refreshes at the ms rate.

Haven't tried with debugging disabled, but how would that differ from having a sequence or not?

[altenbach]

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@Foreshadow20 wrote:

Haven't tried with debugging disabled, but how would that differ from having a sequence or not?

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At the moment we are on a witchhunt because your observations make no sense. At such a stage, all we can do is randomly change other things around and see what happens. Maybe we can find a pattern after a while. Are there any allocation dots? What if you insert an "always copy" in one of the wires involved?

[JÞB]

All I can add is ...

You're not seeing what you think you're seeing.

Those uninitialized string shift registers can easily fool you when they have the last runs data in them rather than empty arrays. 

Nesting string driven case structures 3 deep is a questionable practice.   

So, when do those shift registers get initial data and when are they flushed?  Proper init and shutdowns are really a great idea,  unless you want to get different results between runs and can't understand why.

Yeah the time changed because the data was changed not because the sequence was added.

Check out that 8 ball magic!

[Foreshadow20]

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@altenbach wrote:

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@Foreshadow20 wrote:

Haven't tried with debugging disabled, but how would that differ from having a sequence or not?

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At the moment we are on a witchhunt because your observations make no sense. At such a stage, all we can do is randomly change other things around and see what happens. Maybe we can find a pattern after a while. Are there any allocation dots? What if you insert an "always copy" in one of the wires involved?

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Disable Debugging increases the speed slightly, for both implementations (with and without the Sequence).

I tried the "Always Copy" in the case shown in the first post as well the final write of "TC" into memory. It made no difference.