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Applying dither to proportional valve control in cRIO

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Hello Community,

 

I'm involved into a project of a test stand for valves testing - solenoid proportional valves control will be needed.

We are going to use cRIO with AO modules and utilize FPGA target.

Leaving the hardware apart for now, I would like to design the software for applying and controlling dither parameters.

 

On which target (RT or FPGA) the dither should be added to the control signal?

Can you recommend any solution (design pattern, function, library) for applying dither to the valve control signal in cRIO?

If not - how should I start?

 

Thanks for Your time.

Darek  

 

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Hi Darius,

 

can you explain the term "dither"? What do you want to implement here?

 

Do you want to implement image processing algorithms when testing valves?

Best regards,
GerdW

using LV2011SP1 + LV2017 (+LV2020 sometimes) on Win10+cRIO
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Hello GerdW,

 

Thank you for your interest!

 

Dither is a very unlucky name as it introduces confusion - in valves control it's a different thing than in audio/graphics processing.

In valves control it's a high-frequency low-amplitude AC signal superimposed on the DC control signal.

It's added to improve valve performance (reduce stiction, histeresis etc.).

 

Here is the definition:

https://people.mech.kuleuven.be/~farid/tribology/friction/comp/techniques/dither/dither.htm

 

We can assume that I need to add low amplituide sine/square wave (around 100 Hz) to my DC control signal.

Frequency and amplitude of the dither should be adjustable "on the fly" - cannot be fixed values. 

My control DC signal will start from 0, afterwards ramp up to the desired level followed by ramp ramp down back to 0, the cycle will take few seconds.

I tend to generate the control signal on FPGA - but I'm open to Your ideas.

 

If more details needed - don't hesitate to ask.

 

Darek 

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Accepted by topic author Darius_H

Hi Darius,

 

I guess I would generate that sine signal in the FPGA: you need just 3 values to control that dither signal (enable, frequency, amplitude). The FPGA can easily add your DC value (from RT host) with the sine dither value…

Best regards,
GerdW

using LV2011SP1 + LV2017 (+LV2020 sometimes) on Win10+cRIO
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GerdW,

 

Good to hear that the solution is pretty straightforward.

Any problems forseen with the approach as below?

I'm a cRIO beginner and the hardware is not available yet, so please forgive me my trivial questions Smiley Wink
dither_adder.png

 

Best regards

Darek

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Hi Darius,

 

I would add an Enable option to the sine generator signal to be able to disable it's output (for safety reasons). Only output the sine wave when you explicitely  enable it…

Best regards,
GerdW

using LV2011SP1 + LV2017 (+LV2020 sometimes) on Win10+cRIO
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Hello GerdW,

 

Thank you for the solution.

Appreciate your commitment and quick responses Smiley Happy

 

If needed, I'll reopen the the topic once the hardware and dither specifications will be available.

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