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Analog to digital converted amplitude varies using crio and NI9223 and NI9239

Dear community,

 

I found a problem that quite likely is responsible a poor performance of a lock-in implementation in Labview.

 

Let me illustrate the problem:

I directly feed a sine wave (0...3 V) from an analog output module into the ADC and define this to be the science signal. The science signal, when sampled by the ADC, is slightly (< 0.1 %) varying in amplitude (see attached plot, which is a the ADCed sine wave (absolute values)). This is an effect introduced by the ADC itself. When in the lock-in process this signal is multiplied with a perfect sine wave at the reference frequency (the local oscillator), then there are periodic variations in amplitude being introduced, i.e., a sort of artificial noise. It is especially pronounced using the NI9239 with a period of ca. 1 s and less strong using the 1 MS/s ADC NI 9223 with a 20 ms period. Due to the higher frequency of this "amplitude modulation" I get much better results using the latter.  Am I provoking this or is this behavior avoidable? Thank you for your input!

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Message 1 of 6
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When you sample a signal (the sine wave in this case) and the sampling frequency is not an exact integer multiple of the signal frequency, you will get some variation in the phase of the samples. One one cycle a sample might occur at exactly the peak amplitude while on the next cycle the sample nearest the peak might be displaced a few degrees, which results in a lower amplitude for that sample than the actual peak of the signal.

 

Mathematically the Fourier transform integrates over infinite time and those differences are smoothed out. With a finite data set, which you always have in a computer, some of that variation may remain.

 

Of course when the reference signal and the signal being measured are at slightly different frequencies, the multiplication process will gnerate a beat note. Essentially the amplitude variation I discussed in the first paragraph is a also a beat note between the signal and the sampling frequencies. From looking at your data image it appears that the frequencies are drifting with respect to each other as the period of the amplitude variation is quite different in the cylces shown.

 

When you use the higher sampling frequency you may be getting better results simply because you have more data to process.

 

What is the actual sgnal frequency? How fast does the amplitude change? How much noise or interfering signal is present at the ADC input?

 

Lynn

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Hi Lynn

 

thank you for the reply (which was incredibly fast). So it is a beating between the sampling frequency and the signal frequency?

 

The perdiod of the "beat" (which seems to vary) in the image is around 2e5 so 4 s or so (sampling rate is 50 kS/s). To avoid any confusion, the data in the image is just the sampled sine wave, nothing else. This sampled sine wave has a 1kHz frequenzy, so a factor 50, which is not very close to 1 kHz (overtone?...)... I will think about it.

 

I have attached a siomilar figure as the first, but for the 1 MS/s ADC sampling the same 1kHz sine.

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I think you are seeing beating.

 

Note that a 1 kHz signal sampled at 50 kHz has one sample every 7.2 degrees. Cos(7.2) = 0.99211. So a variation in the largest sample per cycle of ~0.008 is to be expected. At 1 MHz sampling the corresponding values are 0.36 degrees, cos(0.36) = 0.99998, and variation ~0.00002.

 

If the frequencies are not synchronized - either derived deterministically from a common source or coupled via a phase locked loop, some difference from ideally synchronous sampling will occur.

 

Lynn

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Thank you very much for your help Lynn. Sounds plausible. What strikes me though is that I assumed the ADC and the signal generation to be synchroneous to the 40 MHz FPGA clock, but they are apparently not.

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From a quick look at the NI 9223 and NI 9239 specifications and manual it appears that each has an internal timebase with some capability for external synchronization.  The internal timebase for the NI 9239 is specified at 12.8 MHz +/-100 ppm.  From the data sheet it is not clear what the permissible range of external timebase frequencies is.

 

If you did not specifically program everything to use the same clock, each module is probably using its own internal clock.

 

Lynn

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