An FPGA clock is out of the correct CLIP Clock range.

[Brian.S]

Hi, I'm quite new to LabVIEW and I can't seem to make any headway.  I'm working in LabVIEW 2010 and I have the LabVIEW FPGA software installed as well.

I'm trying to just put something on my PXIe-7965R but can't seem to get my clocks to work.  I'm using the VHDL code given here http://zone.ni.com/reference/en-XX/help/371599F-01/lvfpgahelp/fpga_clip_clock_ex_code/ in an attempt to just get the software to comunicate with the hardware.  I've created and added the CLIP file to my project, but I'm still getting an error.  I feel that the problem is with a 200MHz clock.

I'm not sure if this is part of the default settings or not, but I can't seem to get rid of this 200MHz clock.  I have the default 40MHz clock selected under the FPGA target properties as the top-level clock, and have no aditional clocks added in my Project Explorer window.  I am using a newly created blank project.

The problem is with the IO Module (NI 5761) (at least that's where the exclamation mark is).  When I go to the Clock Selection tab in IO Module >> Properties, it lists both the 40MHz clock and the 200MHz clock clocks; the pulldown tabs next to them allow me to select either Top-Level Clock or 40MHz Onboard Clock.  In the status message below, it says:

An FPGA clock is out of the correct CLIP Clock range.

CLIP Clock: Clk200   Minimum Rate: 199 MHz  Maximum Rate: 201 MHz

FPGA Clock: 40 MHz Onboard Clock  Rate: 40 MHz 

I'm assuming it's the 200MHz clock, but I can't seem to find a way to get rid of it and frankly, there isn't much I can do if I can't even compile and download code onto my FPGA.  I've searched through several of the pages of clock questions, but none of them seemed to answer what I'm looking for.  I'm assuming I'm missing some basic step or making a rookie mistake; if more information is needed, don't hestiate to ask for it.

Thanks in advance for all your assistance,

Brian Sloan

[Ben_S · Accepted solution]

Brian,

Hello!

The reason you are seeing the yellow exlamation mark on the NI 5761 FlexRIO Adapter Module in your project is because it is not properly configured. In this case, the improper configuration is the lack of a 200MHz clock being provided to the Adapter Module. That clock selection window that you see with the drop down boxes for the 40MHz and 200MHz is actually asking you to specify the source of these two clocks, which are required by the Socketed CLIP of the 5761. You can see that these clocks are required by looking at the help documents for the Adapter Module CLIPs the LabVIEW Help.

LabVIEW Help Path to the CLIPS:

Description of the Signals:

 

To resolve this issue, you will need to create an additional 200MHz base clock in your FlexRIO Project and then choose it as the source of the 200MHz clock required by the Adapter Module.

FlexRIO 5761 Project with 200MHz Base Clock

Selecting that Base Clock in the Dialog Window

 

Additionally, It can be very helpful to start by looking at some of the examples we have for the 5761 Adapter Module. These examples will show you the proper setup/configuration of a 5761 Project as well as provide you with some working code to verify hardware operation. These can be found in the NI Example Finder which can be accessed by choosing "Find Examples" from the getting started screen or Help Menu in LabVIEW.

Accessing Example Finder

Finding the 5761 Getting Started Example

I hope this helps! Please let us know if you have any additional questions.

[Brian.S]

I love you so much right now.

For future projects is there a way to remove the 200 MHz clock, or is it a required part of the process?  Is that due to the hardware I'm using, or is it a default part of the software?

[Ben_S]

Brian,

Glad to be able to help!

In this case, the 200MHz clock is a required input to the Socketed CLIP for the 5761 Adapter Module. The CLIPs for other adapter modules may or may not require this (or any) additional clock(s) for proper operation.

In this sense, it's not necessarily the hardware that you are using, as much as the Socketed CLIP that interfaces the 5761 hardware to the FlexRIO. 

[Brian.S]

Ah I see, thanks a ton for your help, everything works now.