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Alternative to DMA transfers from Host to FPGA in cRIO 9004

Hi,

We are using a cRIO 9004 + 9104 FPGA Chassis + 8x NI 9505 modules to replace an 8 axis Scorbot educational robot controller by a cRIO, but we found some troubles:

- We are using FPGA IPs for Encoder reading, PWM signal generation and PID control, for the 8 axis. This is done using 3 SCTLs for each axis: one SCTL for encoder reading, one for PWM generation and one for NI Softmotion Splines and PID position control.

The FPGA VI is successfully deployed.

- We are using the NI Soft motion in the Real Time controller for trajectory generation and user interface. We are not using another VI on the Windows PC for user interface, just the Real Time processor.

Here we get the R-T error -63001 (NI RIO FPGA Communications) when deploy the Real Time VI. It seems that our controller doesn't support DMA transfers from the Host to the FPGA.

 

Questions:

- If we cannot use DMA transfers from Host to FPGA, is there any other way to communicate the Host to the FPGA avoiding the R-T error -63001?
- Is a good idea to use indexed IPs to reduce the amount of SCTLs in the FPGA to just 3 (instead of 24 SCTLs)?
- Do you have any suggestion?

Regards,

Manuel

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You can use FPGA front panel controls for transferring data from the host to the FPGA. On the host side, use an FPGA Read/Write method to set the value of a control on the FPGA's front panel. You can use a boolean control, or an interrupt, for handshaking - to signal that there is new data available. More details on this technique are available in the FPGA help, examples, and on the NI site.

 

If your FPGA design fits, and you're happy with the performance and maintainability of the code, then there's no reason to try to consolidate loops. One thing FPGA does very well is parallel processing. Unlike a standard CPU, there's no overhead or disadvantage to adding loops because multiple loops really do execute simultaneously.

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You should be able to use the Read/Write Control, to read infromation off of the control of a VI on the FPGA.

They are much slower than then FIFO's though, so this might affect your results if you need hight throughput.

 

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@df86 wrote:

You should be able to use the Read/Write Control, to read infromation off of the control of a VI on the FPGA.

They are much slower than then FIFO's though, so this might affect your results if you need hight throughput.


Whether they are slower or not depends on how much data you are transferring, as has been discussed recently: http://forums.ni.com/t5/LabVIEW/Zynq-7000-performance/m-p/2531694#M768222

FIFOs have higher throughput, but front panel controls have lower latency.

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Hey there.

 

Indeed cRIO 900x series does not support DMA transfers from the Host to the FPGA; that is the reason you are getting an error 63001.

However it does support data transfer from the FPGA to the Host You can find that information in this KB.

 

To transfer information from the host to the rt and to the fpga you can use:

 

Host <--> RT

Network shared variables

TCP

UDP

Data socket

 

RT --> FPGA

Front panel communication

 

loc_bd_fpga_simple_host_api.gif

 

FPGA -->RT

User defined variables

Direct memory access

DMA FIFOs

 

I added some links with examples of each type of communication

 

Hope this info helps

 

Good luck

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