Hi, I will use LAbView to manipulate the FPGA, I want to acquire and separate fetal ECG from the maternal ECG. I have two SCB-68, NI PXI-1033, NI PXI-7841R and DAQ 6009 and of course labview 8.6. For this I have to do this with different manner and compare them: 1) I will use different algorithm in LabView to calculate The fetal heart rate, the amplitude of each wave form and the duration 2) I will do the acquisition of the signals with different way using: First, I have to try to acquire 2 signals (for example sinus and square signals combined) and separate them with the appropriate algorithm Second, I have to test the separation of fetal ECG and maternal ECG signals (simulate signals) that I find in the NI example (can I use them with the FPGA? and how?) Finally I have to use a real signal - From data base (But I have a problem in installing biomedical startup kit and I'm waitting to solve it) - From pregnant women (But up to now I didn’t find a woman which accept to go with me to the search laboratory because they afraid) with SCB-68. That’s why, I thought if I will bring the hardware to the hospital may be I improve to chance to find women accepting this or I thought to use the SCB-68 to instead to transport all the hardware. 3) Before beginning the acquisition I want design the possibility choosing the acquisition mode, single (one electrode for the abdominal ECG and one for the thorax ECG) and multichannel acquisition (I hope to obtain 20 channels acquisition and after I supress the noise signal but I thougut it impossible with my FPGA. Otherwise, for example 8 electrodes 5 abdominal and 3 thorax and having the possibility to changes the choice 6 abdominal and 2 thorax….An message appear to ask to operator tochoice which to he want to select) I try to do the acquisition block diagram FPGA (following the example video and example which work correctly with one acquisition) by two cases: with FIFO DMA and with IRQ but I didn’t know what to change to obtain two acquisition instead one showing by the example, to do block diagram do I have to repeat each time (new project, choose Input output,…..? in the term to compare the different manner (simulate signal and real signal), i need to do different project for each case, I want to find some way to copie the block biagram of the FPGA to win time instead to re make each time a the main block biagram of the FPGA (the "copy" work with the block diagram only in the host) For FIFO method and IRQ method could I have to use two FIFO (or two IRQ in the second case) and changing the size from 32 bits to I16 or U16? Or I have to repeat the bloc as much as the number of acquisition? And also do I have to change the proprieties of the clock timer and tick counter from 32 to 16 bits? Please find below the attachments. For FIFO method, I didn't change any things compared to the original example I just added two acquisition instead one but it didn't compilate correctly. For IRQ I just changed the loop timer to 16 bits in the FPGA block diagram, and the compilation work correctly but I find problem in host block diagram. Thanks a lot to help me <

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