Accelerometer measuring problem with LabVIEW and cRIO

[Tschabee91]

Hi there! 

I have a problem with a school project I'm working on. The situation is that we have to measure the signal of an accelerometer. It's connected to a power supply/coupler, wherefrom it's connected to a NI 9221 module's AI0 port. The 9221 is in a cRIO-9074 which is connected to the PC with Ethernet. We checked the accelerometer with an oscilloscope, that's OK.

With LabVIEW I wolud like to display the signal on a waveform chart. So I've created a real-time project, and added the cRIO-9074 and the 9221 in it. I dragged and dropped the AI0 in the VI where the signal is connected on the module and connected it to a waveform chart.
If I run the VI there is somekind of signal, but it's not what it should be. I can set the number of pulses /min, by setting the revolution of the electric motor whose shaft keeps hitting the rod (which on the accelerometer is glued) once a revolution, so I know what kind of signal form should I expect. But the expected and the result signal doesn't match at all. I expect rhytmically iterating pulses, but what I see isn't rhytmical at all, and the positive/negative peak value of the signals aren't nearly constant too. It looks like it's almost random. I have the feeling like this is a sampling synchronization problem, but I don't really know. It seems like that the sampling of the module and the software only meets randomly, and that's why I rarely get one-one good pulse form on the chart. 
I tried to put the whole thing in a TimedLoop and set the Source type to: Synchronize to Scan engine, but it didn't help. I tried to change the value of the Period and Priority too, but it didn't change nothing. I also tried to change the parameters of the Scan engine in the MAX at the properties of the cRIO-9074, but it's the same situation. 
Another thing is I tried to save one measurement file to the cRIO's memory witht the Write to Measurement file. When I tried to open it I saw, that there are only about 200.000 samples in it, although I have measured for mor than 3-5 seconds. As I know the 9221 has a 800kS/s sampling rate so I have no idea. 
I would be grateful if anyone could help me with this problem, because I'm running out of ideas, and I can't step forward until we can't measure acceptable results. 

Best regards, 
Tschabee91

[ValkoA]

Dear Tschabee91,

you will not be able to access the full sampling speed of the 9221 using this method. If you place the AI0 in a real-time project, you are using something called the Scan Engine (here's a whitepaper with detailed description). In essence, Scan Engine has the current value of your AI channels stored in a variable, and that variable is updated periodically by the CPU. The speed of acquisition depends on the Scan Engine rate, which can be anything between 1 Hz and 1 kHz.

Since you need high speed acquisition, you will need to acquire data using the FPGA, then transfer it to the Real-Time system in chunks. Here you will find a good teaching example on how to do just his. If you are unfamiliar with using FPGA and Real-Time targets, I also advise you to check out our Developer's guide, and this link contains a hands-on to get you started. 

Best of luck with your application!

Regards:

[Tschabee91]

Hi Andrew, 
Thanks for your help, I think this will be very useful! So I need to start the whole thing in FPGA, not Real-Time. I will try to fix the problem whith these information and I will respond about the results.
Unfortunately I can't view the thirdlink you gave. It seems you linked the Developers' guide twice. I can't view the teaching example you mentioned here: " Here you will find a good teaching example on how to do just his" 

Tahnk you for your help! 

Regards: 
Tschabee91

[ValkoA]

Dear Tschabee91,

Indeeed I have miscopied the link. Here is the correct one.

Kind regards:

[Tschabee91]

Hi Andrew! 

We tried out to build an FPGA measurement based on the example you linked me. It work much better than a real-time timed loop. Now after compliing to the cRIO-9074 I can see the information on a waveform chart in the host vi what is read fom the FIFO. I can also save it whith Write to Measurement File, and I can open it with Excel or DIAdem. 
I'm very happy that this works, and I thank you very much for your help, but e have some problems though: 
The module what we use can get 800kS/s (NI-9221). Measuring for about 4 seconds, the saved .tdm file only consist at about 1049000 samples. That's about 260kS/s, and that's not too high-speed data acquisition . I've tried to set different things that I could, such as: Looptimng in the FPGA vi, Timeouts at the FIFO's icon, Number of elements, the Depth at the FIFO. Configure Invoke method (this helped a little bit, I had a bit more samples with this), but nothing really helped. I even tried to increase the Requested Number of Elements to 800k at the properties of the FIFO in the project, but this gave me an error at the end of the compliing. I even tried to increase the clock of the FPGA to 200MHz, but this gave me an error too. 
So we don't really got an idea to increase the number of samples taken per each second. This may be a Sampling frequency problem, because we would need more samples in a second but we run out of ideas in school.  And if we open the tdm. file in DIAdem and focus on one good looking part of the graph, we can see that's from only 7-10 samples. 
I attach some pictures of the program that I wrote, such as the project, the host  vi on the computer (alap_jo_1.vi), the FPGA vi on the cRIO (alap_proba_1.vi), a picture of the FIFO's properties and a picture of the sample part viewed in DIAdem. 

I can't even thank you so much for your help, but can you give me some advice, how can we solve this problem? 
Regards: 
Tschabee91

[Tschabee91]

Here are some more pictures that I've been taking about.

[Tschabee91]

And here's teh picture of the project.

[thoult]

Some suggestions:

- the timer in the FPGA code should be set to give you the desired sampling rate that you're after. Set to microseconds, you'll only be able to achieve 1 MHz, 500 kHz, 250 kHz loop rates (etc). Set it to tick counts instead - you know what your FPGA timebase is, and calculate the number of ticks to wait accordingly. For instance, my sbRIO is clocked at 40 MHz, and I want to acquire data at 100 kHz:

Tick time = 1 / Clock Rate

Acquisition interval = 1 / Sampling rate

Desired number of ticks = Acquisition interval / Tick time = 40 000 000 / 100 000 = 400 ticks

This means the FIFO will be filled at the correct sampling rate.

- Check to see whether your FIFO is timing out on the target (the Timed Out? indicator on the FIFO node). If it is, you're writing elements to the target to host DMA quicker than you can pull them out, or in greater number than you've allocated.

- Your host will try to retrieve 10 000 elements every 10 ms. At 800 kHz, you will be writing 8 000 elements into the FIFO in that time period. Either match the two together, or use a FIFO Read with 0 wired to Number of Elements and pass Elements Remaining to the Number of Elements terminal of another FIFO Read node. This will allow you to take whatever's in the FIFO and write it to file. You can use the same trick to empty the FIFO during the initalisation of the FIFO to make sure there's nothing else from a previous iteration in there - FIFO Stop at the end will not empty a Target to Host DMA FIFO.

[Tschabee91]

Hi, thoult!

Thank you, for you're suggestions! I think I'm getting on to what you say, but, just in case could you show me an example of you're last suggestion? I don't really understand yet the emptying FIFO with the two FIFO Read nodes, but if there would be an image of the empty and read FIFO with two FIFO Read Nodes, I would be really glad. 

Thank you for your help and kindness!

Regards: 
Tschabee91

[thoult]

I'm at home, where my home installation of LabVIEW has no FPGA module installed, but here's an image I've cribbed from here.

The orange while loop contains two FIFO Read invoke nodes. The first has 0 wired to the number of elements to read; the second has the number of elements wired to the elements remaining output of the first one. This retrieves all elements in the FIFO at that moment in time.