Abort Multiple Parallel Loops in FPGA Environment

[grkr]

Hi all,

I have developed a LabVIEW FPGA code that runs two parallel loops.  The first loop monitors external positioning sensors, and the second loop provides the control algorithm for the system under test.  I am trying to incorporate a "kill" condition based on the external positioning sensors that operates in a fashion that is similar to the abort button on the LabVIEW toolbar, but I have been unsuccessful in finding a solution based on local variables/notifiers/etc. in the FPGA coding environment.

Unfortunately, I cannot provide the direct code; however, the control algorithm loop contains a rather lengthy sequence structure inside the while loop, which would need to be terminated immediately upon reaching a sensor threshold reading.

Does anyone have a suggestion about how to implement such an abort command?  I really appreciate the help, and if I can provide any additional information, please let me know.  Thank you very much.

[nathand · Accepted solution]

You'll need to replace the sequence structure with something that can be interrupted.  The simplest solution is a state machine: you put a case structure inside a while loop.  The while loop contains a shift register indicating the current state.  Move each frame of the sequence into a separate case.  Then, add some logic that checks if the abort condition has been reached, and if so, go to an "abort" case instead of whatever the shift register contains.

[grkr]

nathand,

I have been processing your response for a number of minutes now, and, while your idea certainly creates an abort checking condition that is close to desired, I am concerned that what you describe would not "kill" the program mid-case in a given step of the sequence.  For instance, if frame 1 of the sequence takes 10 seconds to complete, and I issue an abort command after 2 seconds, the abort command will not be registered until after the 10 second frame (although every other frame in the sequence would be aborted).  If I am understanding this correctly, this is not optimal; though, it is much closer than having the full sequence execute.

[nathand]

Correct - you can't interrupt a frame in the middle of execution.  You may want to break up your algorithm into smaller pieces so no step takes an excessively long amount of time.  If you have a step that's waiting with some long timeout, set the timeout much shorter and execute that case repeatedly so that you can check for the abort condition as well.

I'm assuming here that you don't want to abort the FPGA execution entirely.  If that's actually what you want, you might consider passing a flag or interrupt to the host VI, which would then call the FPGA Abort method.

[grkr]

The solution presented certainly works as implemented.  I have been pondering a simpler method than using a bunch of case structures, but it seems that the best course of action on the FPGA is to create the state machine logic as you stated.  Thanks for the help; I appreciate the quick responses.