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AO runs ahead of DO in cRIO

Hi, 

 

I'm now testing NI9401(DO) and NI9264(AO) with cRIO and had read the FPGA-example of the modules.

 

But now there's some problem. In my attach files, "FPGA 0--Test DO.vi" shows that a Wait Vi and sequences use about 100us, that's larger than my desired sample rate. And FPGA-example, the answer of community shows I should use Timer Loop with Sequence Structure.

 

1. In "FPGA 1--Test AO and DO.vi", with two Timer Loop, AO and DO gets a good synchronicity, I see 7us with oscilloscope.

 

2. In "FPGA 2--Test AO and DO.vi", It seems some AO runs ahead of DO. Such as, with time sequence(all time unit is 1ms), t1, t2, t3, t4, t5..... AO0 always ahead of DO0 t1 and DO0 keeps synchronous with AO1(with oscilloscope). Howerver, when all Timer Loop replaced by Wait, it's true, which is the same with original code maker.

 

There's time sequence A, B, C. I want to realize that B is divided into Ndt, and, every dt, it has a independent values. So the messy part of block diagram is doing this. 

 

I wonder that in a while loop, the three part is parallel,  why is AO0 running ahead of the schedule from the oscilloscope, or I should Initialize the Timer Loop, even that the Timer Loop is not suitable for a nesting of "For loop, Sequences Structure"?

 

Thanks.

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Hi mhsj,

 


@mhsj wrote:

2. In "FPGA 2--Test AO and DO.vi", It seems some AO runs ahead of DO. Such as, with time sequence(all time unit is 1ms), t1, t2, t3, t4, t5..... AO0 always ahead of DO0 t1 and DO0 keeps synchronous with AO1(with oscilloscope). Howerver, when all Timer Loop replaced by Wait, it's true, which is the same with original code maker.


You should not use stacked sequences, especially not in FPGA code:

This is the main loop in your FPGA-Test2 VI after flattening the sequence.

 

There are two problems:

- those 3 parallel IO loops/sequences aren't synchronized very well. While the FPGA will execute them in parallel there is no guarentee it will start them at exactly the same clock cycle. Additionally the wait functions might receive different values…

- you try to access channel AO0 and AO1 with different IO nodes: this most often leads to delays between the channels when outputting those samples! To have the minimum delay between those samples you should use only one (1) IO node to output both channels AO0&AO1!

 

General problem: only use pure English ASCII chars (just A-Z, a-z, 0-1 with some other chars in the ASCII range from 32dec/20hex to 127dec/7Fhex), otherwise we (your worldwide audience) might get into trouble editing/running your code. As you see in the image the labels/names of the modules are rather mangled…

 

General advice: avoid division functions in the FPGA. You can easily divide the data in the host/RT before sending it to your FPGA!

Best regards,
GerdW


using LV2016/2019/2020 on Win8.1/10+cRIO
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Thanks for taking the time. Then I change the stacked sequences to sequence structure, howerver, the problem still exists.

 

Here I restate the problem with my new test:

1. I was cheated by the "FPGA 1--Test Do and AO.vi". With that structure, for example, inputing time sequence t1, t2, t3, ..., tN, DO and AO outputs with order t2, t3, t4, ..., tN, t1. So they seems synchronized. Because they all discard the first time interval.

So in a For loop, a  sequence structure, with first frame of loop timer, second FPGA/IO, it  ignore the first time interval of the hole while loop. But I don't know when the loop timer reset.

 

2.And "FPGA 2--Test DO and AO.vi"(fixed by your advice,check.png), DO0 ignore the first time interval as well.For example, t1, t2, t3, t4, t5, with DO T,F,T,F,T. The result is F(t2), T(t3), F(t4), T(t5), T(t1). This is true in oscilloscope. And AO1 goes the same.

But AO0 has several For Loop, so it's discard more time interval.

And I wonder that what about the next while loop? AO0 ignore more, means that it walk through the timeline in advance, so in this time, the loop timer of AO0 reset now? Or after DO0 and AO1 complete the timeline, they reset together?

In oscilloscope I see that AO0 is still ahead of DO0 of t1.

 

So the question is that, even use for loop and loop timer, they ignore the first time interval, how should I use it?

Such as, I want to in t1, t2, t3, t4, with output A1, A2, A3, A4, I transfer an array with 4 number, by for loop, I can easily align. But it ignore t1, I should transfer 0, t1, t2, t3, t4 with A1, A2, A3, A4, A4?

 

I've tried to use one FPGA/IO to AO0 and AO1, bu

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Hi, 

 

By using a case structure and an extra time, I can use the Loop timer to timing.

 

For example, I want to the AO output A1, A2, A3, A4 at t1, t2, t3, t4, then I use a for loop and loop timer,then input is 0 t1, t2, t3, t4, the input AO is A1, A2, A3, A4, 0. When the For loop run for the fifth time, the value of 0 is not  transmited to AO. This works well in the oscilloscope.

 

Then I add 3 ports in my FPGA.  AO0, AO1, AO2, it's almost synchronized, about 20us.

 

Howerver, I add the fourth ports, AO4, then all the AO is slow then the about 40us, especially in the end, it's slow about 150us.

I think even it has a natrural delay, it' must be less then 100us, at least. Because, even lt call at differenct AO, then time is less then the sweeping time(Accessing the FPGA/IO) times the AO number, which is small.

 

My AO card is 9264, and I have to give a different value for different AO, so I split the FPGA/IO. By one FPGA/IO, it's impossible to set a different time.

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Hi mhsj,

 

please keep your discussion in one thread - it is still about the very same problem!

 


@mhsj wrote:
How to elimate the delay of my code and Can I set a priority?

You eliminate the delays by joining all those IO nodes into just one.

And on FPGA you cannot set any priorities…

 

Your code still uses a lot of non-English chars and so making it very hard for us to edit/debug it. Why didn't you change that in the meantime?

It also does NOT HELP to increase the size of the blockdiagram: it makes your code even harder to read/analyze!

 


@mhsj wrote:

My AO card is 9264, and I have to give a different value for different AO, so I split the FPGA/IO. By one FPGA/IO, it's impossible to set a different time.


Why do you think so?

You can set all channels using just one IO node in a loop at a fixed time interval. And you can change the values for one, two or all channels from one iteration to the next iteration…

 

Btw. I just checked the example finder in LabVIEW: there are examples just for the NI9264 module to explain some "non default" usage in the FPGA. Did you examine those examples?

Best regards,
GerdW


using LV2016/2019/2020 on Win8.1/10+cRIO
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@GerdW

 

Hi, thanks for replying me again, let me explain all.

 

1. Maybe you think it's the same problem, but actually I didn't get any advice on last discussion and nobody reply to my newest answer. Maybe it's too easy for a labview expert.

 

2. I have no free labview English version, but now I try to borrow one. But I mainly to show the strucure of my code, in this way, it has a delay problem, otherwise, I can't find the solution. In other words, the structure of my testing code is same with the original code, but the original code is too large and has redundant function outside the while loop, so I simplify it.

 

3. Your reply "You can set all channels using just one IO node in a loop at a fixed time interval. And you can change the values for one, two or all channels from one iteration to the next iteration…" is a misunderstanding of my demand.

My demand is that, for example, I want the AO1 maintain the outputs 20us, and AO2 30us, but the next time, the AO2 may be the 40us, AO1 is 30us, how can I use just one FPGA/IO node and one Timer to realize it? I think about for a week. The AO1 and AO2 must go with different timeline, AO1: 10us, 20us, 30us, 40us, AO2: 5us, 20us, 20us, 10us, 25us.

 

4. I've tried to avoid the Sequence Structure, but I have to use a changeable array, such as, the first time, the input is 10, 20, 30, 40, 50, then the next time is 10, 20, 5, 5, 5, 5, 4, 6, 40, 50. I do find any solution for it now.

 

5. Btw, I don't find any NI example code for my demand, in NI example finder, I see "NI XXXX getting start.lvproj", the only one corresponding to 9264 is "NI 9264 Advanced Writing Methods.lvproj", but it's related to the LSB weight and offset, how can it relate to me?

 

6.I've ever searched on google or NI, like "changeable array site:forums.ni.com" or "loop timer"....etc, I didn't see any solution for me, can you please tell me a keyword, then I could solve it by google or existing problem in NI.

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Hi mhsj,

 


@mhsj wrote:

1. Maybe you think it's the same problem, but actually I didn't get any advice on last discussion and nobody reply to my newest answer. Maybe it's too easy for a labview expert.


"Getting no answer" is no reason to start a new thread for the same topic. You can still bump that thread to the top by posting a new message in the thread - after waiting some time! We are (mostly) volunteers, writing in the forum in our spare time…

 


@mhsj wrote:

2. I have no free labview English version, but now I try to borrow one. But I mainly to show the strucure of my code, in this way, it has a delay problem, otherwise, I can't find the solution. In other words, the structure of my testing code is same with the original code, but the original code is too large and has redundant function outside the while loop, so I simplify it.


You don't need to install an English LabVIEW version. Just use only plain English labels in all your code/project, ASCII chars from hex20 to hex7F…

 


@mhsj wrote:

3. Your reply "You can set all channels using just one IO node in a loop at a fixed time interval. And you can change the values for one, two or all channels from one iteration to the next iteration…" is a misunderstanding of my demand.

My demand is that, for example, I want the AO1 maintain the outputs 20us, and AO2 30us, but the next time, the AO2 may be the 40us, AO1 is 30us, how can I use just one FPGA/IO node and one Timer to realize it? I think about for a week. The AO1 and AO2 must go with different timeline, AO1: 10us, 20us, 30us, 40us, AO2: 5us, 20us, 20us, 10us, 25us.

 

4. I've tried to avoid the Sequence Structure, but I have to use a changeable array, such as, the first time, the input is 10, 20, 30, 40, 50, then the next time is 10, 20, 5, 5, 5, 5, 4, 6, 40, 50. I do find any solution for it now.


So the GCD (greatest common divider) of all those delays is 1µs? (Or is it 5µs?)

You could run a loop at a rate of 1MHz (or 200kHz) and set the AO channels as needed…

 

Btw. the NI9264 is specified at 25kS/s, so you should limit your loop/update rates to 40µs minimum!

 


@mhsj wrote:

5. Btw, I don't find any NI example code for my demand, in NI example finder, I see "NI XXXX getting start.lvproj", the only one corresponding to 9264 is "NI 9264 Advanced Writing Methods.lvproj", but it's related to the LSB weight and offset, how can it relate to me?


That example is not (only) related to reading the LSB weight/offset, but also shows how to efficiently write samples to the AO channels at a variable rate…

Best regards,
GerdW


using LV2016/2019/2020 on Win8.1/10+cRIO
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