I have a cRIO and 9221 modules.
I have created an application that is simultaneously sampling 8 channels on FPGA (FPGA.png) and then interleaves it to send it to RT target.
RT target fetches is using the code in RT.png. DMA FIFO has a buffer of 160000 elements. RT fetches data in 16000 sample sets. (basically a 20 ms waveform at 10 us sampling 9221 modules).
What I am observing however when I display the data is that if I have a signal connected to the first differential channel in 9221 module after deinterleaving the transferred data the data for the first channel seam to appear to be from the second channel (instead of being at indices 0 7 15 etc. they are at 1 8 16 etc.). If I remove first 7 elements from the array or ad 1 extra the data is correct. It seams I am always missing the very first sample and this introduces the shift.
How can I debug it or rectify the problem without resorting to the brute force solution of deleting/adding elements?
None of your math seems right to me. The Sampling Delay has nothing to do with the number of samples you should be reading. You should be simply dividing the number of samples available by the number of channels. The Quotient of this will tell you how many samples of each channel have been taken. Then when you actually read, you should read that quotient multiplied by the number of channels samples. This way you make sure you are getting full scans with each read. Otherwise you will get out of sync and then things will look all messed up.
Maybe I was not clear enough.
I made one mistake I am using 9215 modules not 9221.
What I am doing is waiting for the FPGA to have 16000 samples in the DMA FIFO before reading them in one go. I am basically trying to read 20 ms of data. 8 channels at 10us sampling and 20 ms of capture gives me 16000 samples.
Now sending it interleaved means that every 8th sample will belong to Channel 1 (0,7,15....) and so on.
If I decimate the array of 16000 samples into 8 the first output from decimate funstion should be Channel 1 from my rio, second channel 2 etc according to the documentation.
But what I see is actually that somehow after transfer I get the signal from my second phycical channel (on the rio) on the first output from my decimate array function.
And that I do not understand. To my logic rio reads the data and saves them to the array in the order ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch1 ch2 .....
so as long as I read multiples of 8 decimate array should give me correct split.
I mentioned sampling delay and buffer size to show that I have enough spare fifo length to prevent possible overflow and data loss.
One more thing sampling delay for my example is set at 10 and active channels at 8 and input to greater then is set to 1 so a true read of data is performed only if my DMA FIFO contains a full 20 ms of data.
You don't show enough of your code to be able to explain the behavior your describe. Where is the decimation? Why don't you check the number of elements remaining against the actual number of elements you want to read, and remove the quotient/remainder? Do you know that you never overflow the DMA FIFO? You might want to put an indicator (that latches, using a shift register) on the timeout from the DMA FIFO Write. Why so many global variables?