02-14-2014 09:59 PM
I'm programming in LabVIEW 2013, with a cRIO-9068 chassis and a 9206 C series module. The specs on the module are for 250KS/s aggregate, but I'm only able to get exactly half that. I've attached a screen shot of the test code. I've even pipelined the data around to the fifo just in case the fifo loading was interfering with the loop timing. Which of course it wasn't. I've tried 16 channels with differential and RSE, and both times can only get 7.8-ish KS/s, which is 125KS/s aggregate. I tried one channel and could only go down to 8 us before the Actual Loop Time is greater than the Loop Time control. Again, 125KS/s. Is there some setting on the 9206 that cuts the sample rate in half?
Thanks,
DaveT
02-17-2014 06:22 AM
Is there a difference if you use the raw mode instead of FXP ?
02-17-2014 01:01 PM
Hi Dave,
Have you set the Minimum Time Between Conversions setting in the module properties under the project view? Typically this defaults to 8 us and can override your loop timing. This might explain the behavior you are seeing. According to the specs of that module, you will need 4 us to achieve 250 kS/s aggregate. See the link below for details on this.
http://digital.ni.com/public.nsf/allkb/F6A08AB81B312F4D8625790B004D58C2?OpenDocument
If that does not help, do you see the same behavior using the examples that ship with LabVIEW? There are some simple projects specific to the 9206 on a cRIO platform. These can be found under the Example Finder in Hardware Input and Output » CompactRIO » Module Specific IO » Analog Input.
02-18-2014 09:59 AM
David,
Yep, thanks, that was it. Setting the Min Time Between to 4 allowed me to get to 5 us (200KS/s) with one channel, 65 us (15+ KS/s) with 16 channels. Can't quite (yet, maybe there are tweaks left to try) get to the rated 250KS/s aggregate, but close enough for my purposes.
Thanks for your help,
DaveT