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6674T dual chassis triggering

Hi,

 

I have two chassis, and I want to synch the triggers in them.

One is the master routing the triggers to the backplane via PXI Star from the DDS, the second one is supposed to get the Clock In signal ( the DDS of the first chassis ) & route it to all PXI Star terminals and also to clock out.

 

Wrote code, executed it and I see this response on the scope.

I also an attaching my MAX screenshot to explain the hardware set up, basically I'm trying to make two 6674T cards work together to achieve this goal.

 

I'm kind of puzzled... why:

1)      Signals are shifted.

2)      The height isn’t the same…

3)      I don’t like the rising edge of channel 1.

 

Clock Out of PXI1 6674T is phisically connected to Clock In of PXI2 6674T via their front panel terminals.


Anybody has an idea what went wrong here?

 

Any help is appreciated,

Maciej


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After a brief look through your code:  (Warning, it was brief and I do not see the caller)  There is something wrong with the PXIxRouting Constants in the init method of TriggerManager.vi.  They are used in the start method to make multiple routes that just don't really make any sense.  For example: if you do an init-set-start you assign clock in to clock out at 1kHz on the device on PXI2Slot10.  when (from you hardware configuration) you really want PXI2 Clk in going to the backplane.


"Should be" isn't "Is" -Jay
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Hi Jeff,

 

Thanks for replying,

the reason I've routed the ClckIn and ClckOut on the Front Panel of the PXI2 is so that I can Plug the ocsiloscope somewhere so that i can double check my signal what is going on the backplane is ok.

This is actually what was plotted on the scope picture.

 

I'll just explain the connections I have on the Front Panel.

 

PXI1_ClkOut  -------->  PXI2_ClkIn ( Phisical Wire )

 

---------------------------------------------------

 

PXI2_ClkOut -----> oscilosope. ( Phisical Wire )

---------------------------------------------

 

 

Routings: 

 

DDS ---> PXI1_ClkOut

DDS ---> PFI_LVDS0    ( just for debugging )

 

------------------------------------------------------

PXI2_ClkIn  -------->  PXI2_ClkOut 

 

 

 


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