160 counters in FPGA. Use arrays or 160 loops?

[GS]

I need to program a 7811R FPGA module to give me 160, 16 bit counters. Originally I made 4 loops (one for each connector) and put the counts from each loop in a 40 element array - mostly to make it easier to program. I'm wondering if that's a bad idea. Would it be better to use an individual loop for each counter? Or maybe use one array per 8 bit port (20, eight element arrays)? I don't have my board yet so I haven't been able to test it.

George

[AllanS]

Hello George!

Your biggest issue here is going to be gate usage on the FPGA.  First, are your counters all counting at the same rate therefore having the same values?  What are you doing with the output of these counters?  The issue you are going to encounter reguardless if you use one array of 160 elements any other combination you will use a tremedous amount of space on the FPGA.  While loops also take up space on the FPGA so minimizing those is not a bad idea.  If you wish to know more about FPGA utilization let me know but for me to help I need to understand a little more about what your doing.  Have a great day!

Allan S.

National Instruments

[GS]

I want to do one of two things (haven't decided yet which is best) - either get a total pulse count on each of 160 channels or count missing pulses (no pulse within a given time period) on each of 160 channels. If everything in my DUTs is working right, then all channels will be counting at the same rate (probably 1 pulse per second for 2 days). That's all the FPGA needs to do. I'll display the count in my host VI. Is there a tradeoff between using too many loops and using arrays? Or do arrays use up so much more space that I'm better off using loops?

George

[AllanS]

Hello GS!

Now I think I understand you application.  I would do this all in one loop.  Inside the loop I would read in the entire port (all of them) and do analysis on those resulting values.  The only down side to this method is that you will have to do some extra computation to figure out which UUT did not pulse.  Let me know if this is plausible for you.  Have a great day!

Allan S.

National Instruments

[GS]

That should work. So having a 160 element array to pass the values to the host VI is no problem?

George

[AllanS]

Hello George!

A 160 element array would be a problem.  I would work with the 160 lines in terms of ports (8 lines) then you have an array of 20 8 bit integers.  Let me know what you think and we will go from there.  Have a great day!!

Allan S.

National Instruments

[GS]

Now I'm a bit confused. Each counter (160 of them) will have to be a 32 bit integer. How can I hold that much information in an array of 20 8 bit integers? Wouldn't that size array only let me pass back the current status of the line?

George

[AllanS]

Hello George!

I am terribly sorry I misread your previous question.  You want to check for pulses on 160 lines and then keep track of the number of pulses in a 160 element array.  I believe this is the only efficent way todo this but I am concerned whether their will be enough real estate on the FPGA to handle this 160 element array.  Additionally, its going to take some time to read and process 160 lines at the same time.  Therefore you may want to break this up into 20 loops of 8 lines so that you are not waiting for one loop todo all the processing.  This would also give you 8 arrays of 20 elements.  Sorry it took me so long to get on the same page with this issue.  I hope this helps and please continue to write if you have more questions.

Allan S.

National Instruments