Right now, you can simulate the I/O from an FPGA target. Timing features and other hardware-specific VIs are not executed, but the code still functions and allows you to debug certain aspects of it without working through the compile process. It would be similarly helpful if you could simulate the real-time controller, or a cRIO in scan mode, with simulated IO. Again, the resultant VI will not be truly realtime, but it would allow useful development without having constant access to the cRIO.
To allow expansion of DAQ capabilities from a real time PXI Rack it would be nice to be able to add a Compact DAQ chassis to the ethernet port and address it like you can on a desktop. I understand this is possible for USB connected chassis but not ethernet.
This would allow an existing RT DAQ system to be easily expanded, or to acquire data from remote points without the necessity of wiring every channel back to the main rack.
Propongo se actualice el vi "RT Ping Controllers" para las últimas versiones de Labview, funciona muy bien en aplicaciones HOST que comunican a CRIO por ejemplo,he utilizado este vi de la versión 8.6, sin embargo no sé hasta que versión pueda ser soportada.
At my company for all of our real time work, we are starting to use Veristand a lot. It is great that there are so many already available primitives on the Veristand palette within labview which are very useful. However, there is currently no Veristand primitive in Labview, that actually starts the Veristand.exe program itself. You have to use the System Exec to do it. I think adding a Veristand primitive that performs this function would be great.