Make FPGA Bitfile signature and Xilinx IPs version control (git) compatible

[http8000]

It would be great if one could pull FPGA Bitfiles/changed Xilinx IP without recompiling the code / re-configuring the IP cores.

Currently it seems that I need to copy the Xilinx IP via the Filesystem (e.g. network-drives) after pulling a new version from a git repository.

This works since git doesn't detect any change (no commit required), but the modification date is preserved. But it is very annoying.

For FPGA bitfiles this trick doesn't work for me, at least not if the path doesn't perfectly match.

[Intaris]

We work with Xilinx IPCores and SVN, what exactly are the problems you are experiencing? I don't understand the problem as you have tried to describe it.

[http8000]

Hi, thanks for the answer!

Well, you are right. When checking it more carefully it in fact doesn't affect all IP cores, but only one of the "FIR Compiler" (DDS  and CIC work without regeneration).

When trying regenerate the FIR core I get the following error:

** Xilinx Vivado
Resampling.lvlib:interpolat2.vi\FIR Compiler update failed: support files for node Resampling.lvlib:interpolat2.vi\FIR Compiler have been changed. Reconfigure the node manually or revert the change before proceeding.

  

[heel]

Indeed an annoying problem but given the surprisingly low kudo level and that NI prioritize based on this, fix is likely far away.

See this

https://forums.ni.com/t5/LabVIEW/How-to-make-an-FPGA-project-compatible-with-GIT/m-p/4200955#M121638... 

for a discussion of at least some workaround for the Xilinx folder problem.