"Break" VI when FPGA I/O input node is not connected

[BillMe]

Writeable inputs to FPGA I/O nodes can be left disconnected without any warning (or broken VI indication) from the VI in which the I/O node is used. This can cause some vigorous head-scratching if the missing connection is not immediately obvious as in the screen shot below. For obvious reasons, FPGA controls have no connector assignment or "Recommended, Required, Optional" attribute. In that case, and to avoid playing "Where's Waldo" on the block diagram, I suggest making FPGA I/O node input connections implictly "required", and if not, the VI would be broken. This would be the same behaviour as seen with cluster nodes. 

[GerardoG]

I think this is a good idea. Just as a clarification, I believe you meant FPGA interface Read/Write Control Nodes as opposed to FPGA I/O Nodes - which already require their input terminals to be wired.

[SuperDuperCooper]

Similarly, I would like a warning when the index of 'index array' is not wired.

I guess it can be useful sometimes, but it's caught me out more than once when moving code around.

Applies to FPGA and vanilla LV.

[crossrulz]

Do NOT do that with the Index Array.  I very rarely ever wire up the index for that node.

[RavensFan]

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@SuperDuperCooper wrote:

Similarly, I would like a warning when the index of 'index array' is not wired.

I guess it can be useful sometimes, but it's caught me out more than once when moving code around.

Applies to FPGA and vanilla LV.

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You surely must be joking to even make a statement like that!

Do you really want to have to wire up every index input from 0 to N whenever you want to break apart the elements of an array?