LabVIEW FPGA Idea Exchange

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I am looking for a way to transmit 9 bit Address array 17 bit Data Array in a Manchester Format. I am using a PCI-7813R with SCB-68 Interface. I have breadboarded the push pull circuit to generate the +/-5V Signal.

NI has to link to Manchester enable encoding.

http://zone.ni.com/devzone/cda/epd/p/id/6400

http://decibel.ni.com/content/docs/DOC-2824

2nd link mentioned about half bytes and update output state that I do not have an understanding of.

The Problem is since Labview does not work like a Hardware Clock. The Clock in my program does not transition a full period during the iteration. Thus the output is wrong. I have tried Global variables without any success.

I am trying to duplicate the DOC-2824 picture of Manchester Enable Communication.

My Code is attached.

Any assistance would be appreciated.

Greg

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I have several FPGA projects that require significant compile time (up to 1.5 hours), and for that I am thankful to have my compile server running on a separate computer.

The issue comes with the seven Pre-Compile steps that occurs before LabVIEW sends to the code to the compiler. On one particular project this action alone can take up to 35 minutes during which time I can do nothing on that machine.

I would like to see much of this precompile time moved from the development environment to the compile server. There already exists a mechanism for updating the user with the compile status so those precompile errors could be annunciated in a similar fashion.

Get the development system back online as quickly as possible.

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Writeable inputs to FPGA I/O nodes can be left disconnected without any warning (or broken VI indication) from the VI in which the I/O node is used. This can cause some vigorous head-scratching if the missing connection is not immediately obvious as in the screen shot below. For obvious reasons, FPGA controls have no connector assignment or "Recommended, Required, Optional" attribute. In that case, and to avoid playing "Where's Waldo" on the block diagram, I suggest making FPGA I/O node input connections implictly "required", and if not, the VI would be broken. This would be the same behaviour as seen with cluster nodes.

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The NI 9802 (Secure Digital Removable Storage Module for CompactRIO) is a cRIO module that has two SD memory card slots. The problem is that the programmer cannot index the ports as "0" and "1". The solution is to write a code for "0" and repeat it for "1".

The proposal is to allow the user to select memory card by a terminal in the "Method" and "Property" nodes.

Since the maximum amount of memory per card is 2 GB, if more than 2 GB is needed, the programmer should manage to split the data in two cards. Right now the code should be duplicated and selected by a "Case" structure. In many other situations the programmer may need to use one or other card, like when a big file should be saved after the usual check of the available free space in both cards.

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Even though ibberger touched the concept in the idea , I do think that most o people uses LabVIEW under Windows environment. Compiling a FPGA VI happens all in the PC under Windows. I noticed that during this process the compiler uses only one core. Since I'm using a machine with a 4 core processor, the CPU use rarely goes above 25%.

My idea is to update the compiler allowing it to be multicore. The user should have the option to limit the maximum number of cores available to the compiler. This is necessary because the user may want to continue working, while the compiling process is being done in background.

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The first thing you hear about programming FPGAs with LabVIEW is: use single-cycle loops. But if you build a state machine (while-loop + enum + case structure), in many cases you cannot make the outer while loop in a single cycle-loop, because not every state fits into a single-cycle loop. Therefore you have to place the single cycle-loop into every case, which has to run in one cycle, which takes up block diagramm space and is cumbersome. Therefore my idea to create a single-cycle case structure: it uses the same compiling mechanism of the single-cycle loop on every case, which is capable of running inside a single cycle. It would be nice, if this behaviour is configurable, meaning I can decide from case to case, if it is a single-cycle case or not. Some kind of right-click menu options like these: "make this case single-cycle", "make every possible case single-cycle", etc. Of course the mode of the case (single-cycle or not) should somehow be displayed.

Regards,

Marc

Single cycle timed loops are a huge performance enhancer in LV FPGA. We learn to use these very prolifically in and around our code to save precious FPGA space, yet the BD representation of the SCTL is the standard Timed Loop structure, with both the Left and Right "ears" visible as well as the conditional terminal.

I propose that the SCTL be given it's own representation on the block diagram, one without the "ears" and without the conditional terminal (by definition it only runs once). This will promote much cleaner looking FPGA code and more readable diagrams.

When working with alot of fixed point math (think FPGA development), unless you are content to simply let LabVIEW decide what precision you want in your fixed point data types, it is extremely cumbersome to (right click->properties->Output Configuraton->Uncheck Adapt to source......, close window, move to next function and repeat and repeat and repeat. This is especially true if you end up needing to highly optimize your code.

It would be nice to have something like a floating window that could be opened that would display the output configuration data for the selected function or control and allow editing without the need for multiple mouse clicks. The window would automatically update with the configuration of whatever function or control was currently selected.

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LabVIEW FPGA Idea Exchange

Manchester Enable Clocking

Minimize Pre-Compile actions on the local computer when compiling FPGA code

Save FIFOs in a library

Be able to programmatically compile FPGA code

"Break" VI when FPGA I/O input node is not connected

Sort Controls in Read / Write Control (FPGA Interface)

Remove restristions on FPGA target names

Index to NI 9802 port access

Exportability

Connector Name

Multi-core Compiling

dedicated FPGA compile server

Time unit converter for Laview FPGA ...

Configurable timout input unit for Wait on ... I/O method.

RT Node

Configurable single-cycle case structure

Simplify the display of Single Cycle Timed Loops in LV FPGA

Better/Faster access to data representation configuration when working with fixed point math

Add a common part for FPGA Palette