LabVIEW FPGA Idea Exchange

Community Browser
About LabVIEW FPGA Idea Exchange

Have a LabVIEW FPGA Idea?

  1. Does your idea apply to LabVIEW in general? Get the best feedback by posting it on the original LabVIEW Idea Exchange.
  2. Browse by label or search in the LabVIEW FPGA Idea Exchange to see if your idea has previously been submitted. If your idea exists be sure to vote for the idea by giving it kudos to indicate your approval!
  3. If your idea has not been submitted click New Idea to submit a product idea to the LabVIEW FPGA Idea Exchange. Be sure to submit a separate post for each idea.
  4. Watch as the community gives your idea kudos and adds their input.
  5. As NI R&D considers the idea, they will change the idea status.
  6. Give kudos to other ideas that you would like to see in a future version of LabVIEW FPGA!
Showing results for 
Search instead for 
Did you mean: 
Post an idea

Xilinx log window should use a fixed-width font.


Which of these two string indicators with identical content is easier to read?


FPGA Xilinx Log font.png


The one on the left is Courier, the one on the right is the default Application font

It would be nice to be able to use logic operators on arrays in Single Cycle Timed Loops.


I hope the FPGA Register Function Could Add "Find Caller"....





With LVFPGA I work almost exclusively with fixed point numbers, and having to convert my numbers to 8 bits or 16 bits just to use the scale by power of 2 function isn't convienient.



I would suggest to implement the possibility to use at the same time multiple compile servers.

Imagine you have a project with many FPGA targets: it would be useful to send the FPGA vis to compilers working in paraller (a sort of Compiler Farm....).





Having two computers, one for developing and one desktop pc for administrative work, I use the desktop as compile server for compiling the FPGA VIs. The compilation takes about 45 minutes, during which I can't develop anything in LabVIEW. By sending the data to the desktop pc, I can resume my work. Though on the desktop machine it's annoying to always leave this program open and get closed accidentally from time to time or I forget to start it in the morning after booting the pc.



- Minimize the LabVIEW FPGA Compile Server to system icon tray

- Option for starting the Compile Server on booting of the OS. 

I know that when connected to the compile server the local compile status window will show you when a compile is done, however that does seem to severely limit productivity in that the only way you can get back to working in LV is to disconnect from the compile server. The downside is that you don't get any feedback as to when your compile has completed. This is especially true if your compile server is running on a remote machine.


Why not add a feature to LabVIEW to allow disconnecting from the compile server but still provide a background polling feature to update the user when the compile has completed. Something as simple as a dialog box telling me that my compile is ready would be great. It would allow me to get back to work on other sections of the code while still closing the loop on the running FPGA compile process and alerting me that it is done.


If the system polled once every minute or so that would be more than adequate.