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It would be nice if we could use the Atlys board with the FPGA module. As far as i see not alot FPGA boards are suported besides the RIO FPGA boards. (only spartan3e xup) Since these are outdated could drivers be developped for some low cost none NI board ? Preferably the Altys ?
The "FPGA I/O Properties" that can be set for an I/O point under an FPGA target consist of just the name for the I/O point.
On the other hand, the "Shared Variable Properties" that can be set for a similar I/O point under a cRIO chassis are much more extensive and include a description field.
I'd like to see a similar description field included/available for the FPGA I/O points. As it is information that is maintained as part of the "project", the reduced functionality normally associated with an FPGA should not be an issue.
As long as I'm wishing, it would also be nice to be able to export/import names/descriptions/properties from something akin to the "Multiple Variable Editor" for both "FPGA I/O Properties" and "Shared Variable Properties" and if an I/O module is moved from the FPGA level to the cRIO level or vice versa, allow us to transfer or import the relevant properties from one level to the other.
In my old post I was suggesting that the default data type should be changed to FXP (Default data type Fixed Point (FXP)). Since in LV2012 the Single Precision (SGL) is supported in FPGA, this should be the standard data type, not Double Precision (DBL).
I am attempting to write some FPGA code, for a cRIO 9074, to act as a data logger for 50 sensors that I am fitting to a small lifeboat. I hope to save all the data to the 9802 SD card module. From my understanding, it should be possible to take the sensor input signals into the FPGA chip, compile them into an interleaved data group and then output them straight on to the SD card from the FPGA. This means there is no RT controller required; making the system more reliable and quicker. Is this correct? Or is my knowledge wrong?
I have tried to look for some example of this on the web but I am struggling to find any which do NOT use a RT control. Can anyone point me in the direction of some examples?
Few extra details: Sampling frequency = aiming for 10 KHz (will be reduce if system cannot handle it), Input modules include; 9236 strain gauges, 9234 accelerometers, 9205 analogue voltage inputs, anymore questions fire away.
DC to DC converter basics using Labview for VHDL to FPGA Control
I am fairly a novice, that is why simplifications required, before I begin thanks for them who will response in advance
I am designing a DC to DC (Intermediate Bus Converter, a step down BUCK converter, of 24 v input and output 9 v and 5 amp current), By using FPGA controller, having limited knowledge, I need to program this using VHDL, for which I take LabVIEW, but as I am new so do not have any idea as what are the steps that I need to take for implementation, what function that FPGA does in this so that it can generate 24 v and what other mechanisms that have to control inside or outside FPGA that it can give the desired output voltage, if you have any idea about this then I would be glad to receive the steps that are necessary to complete this
The IO Sample Method for the 9205 is very useful in that it can tell the card what channel to scan from two samples ahead, putting the appropriate sample into the pipeline to be read from. Without this method, if one wants to switch channels, the two samples currently in the pipeline will have to be discarded, adding conversion time. With the IO Sample Method, it allows users who know what future samples they want to request to keep up the maximum conversion rate.
I do a fair amount of Pipelining and it would be cool if I could Offset the Input Shift Register from the Output Shift Register.
The default would be to keep them aligned but a right - click would give me the option to offset the input or output Terminal. I think it would be bad form to allow crossing the terminals between multiple Shift Registers so the top Input terminal would correspond to the top Output terminal.
I am looking for a way to transmit 9 bit Address array 17 bit Data Array in a Manchester Format. I am using a PCI-7813R with SCB-68 Interface. I have breadboarded the push pull circuit to generate the +/-5V Signal.
2nd link mentioned about half bytes and update output state that I do not have an understanding of.
The Problem is since Labview does not work like a Hardware Clock. The Clock in my program does not transition a full period during the iteration. Thus the output is wrong. I have tried Global variables without any success.
I am trying to duplicate the DOC-2824 picture of Manchester Enable Communication.