LabVIEW FPGA Idea Exchange

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Working with the NI 5785 our team had a hard time understanding how to use TClk without all of the extra (e.g. streaming) code that comes with the example.


Through support we were eventually put in touch with R&D and they told us how to initiate TClk by setting some of the FPGA controls.  This was helpful but not intuitive.


TClk helps support beamforming applications shown in the NI Marketing but without this usability it is very difficult (impossible) to develop applications promised.


TClk also has other lower level features such as the delay correction.  No info is posted on this either but it is a property we can read.

LabVIEW NXG had the ability to create a resource file.  Though I cannot find the help reference for this I will describe the functionality below:


Right now the Target Scoped FIFO, P2P, DMA-FIFO, Memory, Handshake Items, Registers, Clocks, etc are all stored as part of LabVIEW Project (lvproj) file.


If want to port to a new project file or target I have to copy/paste.  This is not a big deal and works well.  However if I update one project's configuration I have to re-copy/paste.  From a configuration management perspective I cannot ensure the configurations are always the same.  With larger, multi-FPGA projects this becomes critical.


It would be great to have a file that holds all of these resources to allow for easier portability and configuration management.

When we try to compile timing critical FPGA application, if might be failed because of timing violation.

But if it missed only a few nanoseconds, recompiling might resolve the error as below.


Resolving Timing Violations on the FPGA

If your failed compilation misses the required throughput time by only a few nanoseconds, try rebuilding your bitfile. Each build of a bitfile does not always produce identical results on the FPGA, so rebuilding sometimes resolves minor timing violations. 



In most case, compilation might require much time and it's difficult to take quick action after they found the aborted compilation result.

It would be great there is an option which allow automated recompile like below.

Of course the compilation completed, it wouldn't try recompile. Only failed, try to compile again.


** -------------------------------------------------------------------- **

Enable Auto Recompile [  *  ]   Number of Retry  [  4  ]

** -------------------------------------------------------------------- **

Please add the ability to right-click on a Memory, Register and/or FIFO and FIND ALL instances throughout the project and/or VI hierarchy. Ideally it would be just like local and global variables (as shown) for desktop LabVIEW. 


FIND all instances for BRAMs.png

Initially I looked around for my previous idea here: Selecting between two I/O refnums not allowed because I thought it was the same and intended to post a comment to that, but I see that was a bit more specific.


This seems like a more allowable case - why is A forbidden and B perfectly ok?



Select node in SCTLSelect node in SCTL



Case Structure to choose between two values based on boolean inputCase Structure to choose between two values based on boolean input


Here A is forbidden (at Intermediate file generation - so perhaps this would help: Unsupported nodes inside for loop within SCTL should result in a broken VI (NXG != Already Implemented really...)) but B is compiled with no problem. I really don't see why Select of two integers is different to a Case Structure with two integers input, a boolean case selector, and an integer output from the two inputs...


As an idea rather than a rant, I'd like A to be possible.

Xilinx log window should use a fixed-width font.


Which of these two string indicators with identical content is easier to read?


FPGA Xilinx Log font.png


The one on the left is Courier, the one on the right is the default Application font


How amazing yould it be to have the ability to visualise resource usage on a FPGA target using a similar view to that shown above (courtesy of Windirstat)


I only recently shaved a significant portion off my FPGA usage by finding out that I had a massively oversized FIFO in my code for almost a year without noticing.  I feel that this kind of visualisation (with mouse over showing what is actually occupying the space) with differentiation between Registers, LUTs, BRAM, DSPs and so on would greatly aid those of us trying to squeeze as much as possible out of our FPGA designs.


I think providing this information based on the "estimated resource utilisation" i.e. before Xilinx optimises stuff away would be OK.  I'm not sure if the final resource utilisation can be mapped as accurately in this way.


It would also be nice to see CLIP utilisation and NI-internal utilisation at a glance as this is apparently hugely different between targets.



We need a way to simply reinterpret the bits in our FPGAs.  I currently have a situation where I need to change my SGL values into U32 for the sake of sending data up to the host.  Currently, the only way is to make an IP node.  That is just silly.  We should be able to use the Type Cast simply for the purpose of reinterpreting the bits.

All FPGA dialog properties dialog boxes that allow to specify a custom control data type (e.g. Memory, register, FIFO, etc...) should show the path and name for the last .ctl configured. For example,properties.PNG

It would be nice to be able to use logic operators on arrays in Single Cycle Timed Loops.


I just manually transferred a fairly large LabVIEW FPGA project from one target to another (7965R to 7966R).  It would be nice to be able to click on the RIO target in the project and have an option to "Migrate to New FPGA Target" in the context menu.  The menu would open a new dialog where you could select the new RIO target and then it is automatically added to the project and populated the VIs, FIFOs, derived clocks, memory blocks, etc. from the original target.  The user can choose whether or not to delete the original RIO target.


This would also make it very easy for users to transfer sample code from the LabVIEW Example Finder to the correct FPGA target (insead of having the folder labeled "Move These Files").

Single cycle timed loops are a huge performance enhancer in LV FPGA. We learn to use these very prolifically in and around our code to save precious FPGA space, yet the BD representation of the SCTL is the standard Timed Loop structure, with both the Left and Right "ears" visible as well as the conditional terminal.

I propose that the SCTL be given it's own representation on the block diagram, one without the "ears" and without the conditional terminal (by definition it only runs once). This will promote much cleaner looking FPGA code and more readable diagrams.



Hello all.


It is time-consuming that we have to compile all LabVIEW FPGA code even if there is tiny little change on FPGA code.

I understand there is sampling probe, Desktop execution node and simulation tools to reduce such time.


Our customer in Japan, would like to use incremental compile function also on LabVIEW.(Please see below)

I agree his opinion.


What do you think?


Eisuke Ono

Application Engineer at National Instruments Japan.



Many data streams contain information for multiple channels or multiple samples. Today one must pack this data into larger integer types or interleave the data manually into multiple writes to the DMA FIFO API. It would be much simpler if the DMA natively support cluster and array data types. The local FIFO, Memory, and Register APIs already support this; extend it to DMA.

Hi How about facility of import and export of I/O Label in FPGA-Real time project as shown image instead of manually renaming each I/O


IO Label.jpg

When there are many controls on the front panel of the FPGA, selecting the control from a Read/Write Control node in the host can become a pain.  It is one very large list of controls on the front panel of the FPGA.  This list has no scrollbar, no browse, or search feature, and no obvious way of grouping controls.


Here is one example of a front panel, and a video showing how long it takes to scroll through the list of contorls.


FPGA Front Panel.png


And here is the video of me scrolling through the controls:


There is plenty of room for improvement.  Here are just a few ways I think NI could make this better.


Browse and Search


When using a Property Node, or Invoke Node, the very top option is to "Browse..."  From here a list of all properties, or methods can be seen in a resizeable window.  Here you can also search, and sort alphabetically.  The Read/Write Control node could have similar functionality making selection of controls easier.


Front Panel Selection From FPGA


There could be an option for creating a node by selecting the controls on the front panel of the FPGA.  A solution that may work today, is to select the controls, then invoke a custom QuickDrop command that creates the node and puts it in the clipboard so it can be pasted in the host VI.  If this were to become an option, I'd hope there is a way to combine two nodes into one, by concatenating the controls of one onto the other. 


Front Panel Selection From Host


Lets say you already have the Read/Write Control node on the host.  There could be an option by right clicking that would open a new window, showing a static image of the front panel of the FPGA, which the user could then click on.  This would be great because the developer probably already knows the control they want based on the front panel location.  I don't know how possible this is because you could load a bit file which won't have any front panel information. 


Easier Grouping of Controls


Right now there is a way to group controls of an FPGA.  This feature is never talked about, and doesn't work on dynamic bit files.  Here is a discussion where I describe the steps to make controls grouped on the host.  Still this isn't supported on all FPGA setups, and you have to conform to a specific naming convention.  Why can't controls that are grouped on the front panel, just be grouped in the host?



This idea exchange is really for any kind of improvement to the FPGA control selection.

I have several FPGA projects that require significant compile time (up to 1.5 hours), and for that I am thankful to have my compile server running on a separate computer.


The issue comes with the seven Pre-Compile steps that occurs before LabVIEW sends to the code to the compiler. On one particular project this action alone can take up to 35 minutes during which time I can do nothing on that machine.


I would like to see much of this precompile time moved from the development environment to the compile server. There already exists a mechanism for updating the user with the compile status so those precompile errors could be annunciated in a similar fashion.


Get the development system back online as quickly as possible.

This might have already been asked, but I couldn't find any posts.


X-Nodes are huge in comparison to the size of a subvi or most anything else on the block diagram of code, so lets shrink them down.


Can we remove the Read/Write box?  We already have the little triangle to tell us the function/direction.

Can we use the node name instead of the generic term Data/Element?  It's already there.


From there we can model it after a property node using references instead of error lines or we can model it after the IO node which is a little cramped but gets the job done.  Both options retain a purple/pink bar to help identify it's X-node-iness.



The FPGA compilation results should be copied to a file in the folder with the bitfile.  This is needed to track the history of compilation results, especially useful when using source code control.  Right now they get overwritten with each recompile.


Adding a Post-build action VI to the FPGA build spec, would also enable something like this.

When accessing a FPGA control / indicator from the HOST, a ~property node is used, and the developer has to pick the right control / indicator from a list


When there's lots of items on the list, it can be a pain to scan the list for the right one.


At the moment they are listed in order they were created on the FPGA.


Could they instead be listed in alphabetical order? Or give the developer the choice?