From Friday, April 19th (11:00 PM CDT) through Saturday, April 20th (2:00 PM CDT), 2024, ni.com will undergo system upgrades that may result in temporary service interruption.
We appreciate your patience as we improve our online experience.
Parallel loops are supported by LabVIEW but not LabVIEW FPGA, this requires us to copy/paste the same blocks multiple times to make them run in parallel. I would like to see the ability to use parallel loops on FPGA targets as FPGAs are very well suited to this style of programming and the current copy/paste parallelism hinders this.
This is the biggest pain with high channel SCTLs and fully support this! I tried to suggest it as loop unrolling but this description and syntax would make more sense
James Mc ======== CLA and cRIO Fanatic My writings on LabVIEW Development are at devs.wiresmithtech.com
The most useful programming structure on FPGA is parallel execution. I do not understand why this pretty nice notation with "parallel for loops" is available on the host system but not on the FPGA. I have so many cases where the notation would perfectly fit but I have to write it all out and when changing the array size I have to go through all code. NI, you need to give a very good reason to refuse this structure on FPGA or are you just too lazy to implement it 😉 (or do you get payed by the miles of wires we are drawing on the vis?).
programming languages are about how nicely you can express a code!
The best workaround I have at the moment is programming what I want in VHDL and then making an IP block to implement it in LabVIEW. But if I have already programmed up the maths in LabVIEW then I cannot use this work in the VHDL, I have to port the code to VHDL before building the IP.
CLA - Kudos is how we show our appreciation for comments that helped us!
Any idea why this was pulled out? I asked a similar question at the link below, it looks like that would have been a good way to solve it. I wonder if it is worth back-tracking to 2018 for?
