LabVIEW FPGA Idea Exchange

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Parallel loop support

Status: New

Parallel loops are supported by LabVIEW but not LabVIEW FPGA, this requires us to copy/paste the same blocks multiple times to make them run in parallel.  I would like to see the ability to use parallel loops on FPGA targets as FPGAs are very well suited to this style of programming and the current copy/paste parallelism hinders this.

 

 

4 Comments
Active Participant

This would be a big advantage to run reentrant subVIs parallel without copy the subVIs.

 

Parallelizable For Loop.jpg

Active Participant
This is the biggest pain with high channel SCTLs and fully support this! I tried to suggest it as loop unrolling but this description and syntax would make more sense
James Mc
========
CLA and cRIO Fanatic
My writings on LabVIEW Development are at devs.wiresmithtech.com
Member

The most useful programming structure on FPGA is parallel execution. I do not understand why this pretty nice notation with "parallel for loops" is available on the host system but not on the FPGA. I have so many cases where the notation would perfectly fit but I have to write it all out and when changing the array size I have to go through all code. NI, you need to give a very good reason to refuse this structure on FPGA or are you just too lazy to implement it 😉 (or do you get payed by the miles of wires we are drawing on the vis?). 

 

programming languages are about how nicely you can express a code!

 

par.pngpar2.png 

Member

I would love this feature!

 

The best workaround I have at the moment is programming what I want in VHDL and then making an IP block to implement it in LabVIEW. But if I have already programmed up the maths in LabVIEW then I cannot use this work in the VHDL, I have to port the code to VHDL before building the IP.

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