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FPGA resource utilisation visualisation

 

How amazing yould it be to have the ability to visualise resource usage on a FPGA target using a similar view to that shown above (courtesy of Windirstat)

 

I only recently shaved a significant portion off my FPGA usage by finding out that I had a massively oversized FIFO in my code for almost a year without noticing.  I feel that this kind of visualisation (with mouse over showing what is actually occupying the space) with differentiation between Registers, LUTs, BRAM, DSPs and so on would greatly aid those of us trying to squeeze as much as possible out of our FPGA designs.

 

I think providing this information based on the "estimated resource utilisation" i.e. before Xilinx optimises stuff away would be OK.  I'm not sure if the final resource utilisation can be mapped as accurately in this way.

 

It would also be nice to see CLIP utilisation and NI-internal utilisation at a glance as this is apparently hugely different between targets.

 

Shane.

3 Comments
Knight of NI

Anything that helps me find resource issues is a good thing in my book.


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Member

This function would be useful even if the LV IDE just automatically totted up all the elements in the FPGA design using the resource use guide document that NI has already produced!

 

Member

I think there is an option flag for the Xilinx compiler that would add more detail to the compiler reports.  It would be nice be able to turn this flag on or off in the FPGA build properties.

 

Found at the bottom of a Xilinx "toplevel_gen_map.mrp". 

 

Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.