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igagne

FIFO read that doesn't use 100% CPU

Status: New

The FIFO read looks like an event based node (like a dequeue or wait on occurance) and I think there's a lot of people that assume it's going to use minimal cpu resources while it is waiting for data. I'm wondering if we can have an option that behaved like that. For example, could we have fixed sized FIFO read where the FPGA could trigger an interupt to let the RT side know the data is ready?

3 Comments
speleato
NI Employee (retired)

Hey igagne,

 

I think this is a good idea. I get that timeouts implemented with polling are exactly the right thing for some applications, and quite problematic for others. I think having an option would also make the behavior more obvious to the user, which is a good thing. That being said, we do have a few programming practices that we recommend that can help if the polling behavior is not suitable for your application. Have you been able to find a solution that's suitable for your application? What hardware are you using?

 

Along the lines of potential workarounds, I think you'll be interested in this knowledge base, http://digital.ni.com/public.nsf/allkb/583DDFF1829F51C1862575AA007AC792. A couple things I'd highlight, firstly some hardware does already work in the way you've described. Secondly, we generally recommend the example code shown at the bottom of the KB. In this way,your code has control over the polling rate and the tradeoff between a low latency response to data being available and consuming resources on the system. If you wanted an interrupt based solution to reduce time spent polling, it'd be possible to also add a wait on irq node and raise the irq from the FPGA when the data has been written. I'd still recommend polling for data after recieving the IRQ on the host because it's not generally guaranteed that the IRQ will arrive after all the data has made it's way to the host buffer, but it should be a much shorter poll.

 

Thanks,

Sebastian

 

 

vitoi
Active Participant

I guess polling isn't an issue on an FPGA since it takes up zero of the available "processing power". The example at  http://digital.ni.com/public.nsf/allkb/583DDFF1829​F51C1862575AA007AC792 does the trick.

 

Nevertheless, it would be nice to have it as a native feature. Kudos.

vitoi
Active Participant

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