I know this is not easily possible, but if there is a way to emulate FPGA compilation and quickly show the maximum achievable frequency(even approx will do) during development, would be one hell of a feature
Not feasible. The only way to emulate FPGA compilation is to compile.
If you want an estimate, just stop the compilation after the estimated timings arrive. I would agree, however, that an option to only compile certain parts of the compilation would be nice (so that at least manually stopping after estimated results would not be required). Whether such an option would be deemed useful enough to garner support, I do not know.
At least in my designs, the estimated and achieved timings sometimes vary greatly.
