Allow Parallel For Loops on FPGA

[James_McN]

Hi,

I realise that parallel for loops don't work on FPGA because they are designed to create multiple threads which FPGAs don't have.

However lets take the scenario that I have 8 channels of data to process (scale, filter etc.) but do not have time to do this sequentially due to high loop rates.  Could parallel for loops be a way of doing loop unfolding on FPGA rather than forcing me to have 8 parallel paths of identical code?

Cheers,

[srm@viewpointusa.com]

I think you are misinformed about parallel loops on FPGA.  parallel loops run in parallel (by definition) on FPGA.  they will create synchornization access to common resources like I/O but otherwise run in parallel without "switching away" to other loops like regular labview.

The other part of your comment can be implemented on FPGA with pipelining and/or parallel loops.

[T.Hamberger]

I dont understand this answer.

Yes, parallel loops run in parallel on FPGA.

But does there an abbrevieated notation exist for parallel loops containing the same code?

(parallel for-loop with fixed array size (which user James McN wants) would it be - but still not allowed on FPGA;

abbreviated notation would be comfortable to avoid dupilcated code)

pipelining does not solve that problem: as I understood, in pipelining the sequential processment of data through

code parts A, B and C is broken up in different cycles with parallel processment of. e.g. data1 in A, data2 in B and data3 in C

(dataN shifting from A to B to C between the cycles).

Even if A, B and C contain the same code, we would have to make code dupilcation and it does not solve the requirement

that we may need processment of all data (remember: fixed size, e.g. 8 channels) in ONE cycle

[crossrulz]

This idea should really be closed as a duplicate of this one: Parallel loop support