Access to serial and ethernet port in FPGA for cRIO-9068

[JHE]

On the cRIO-9068, the third serial port and the second Ethernet adapter is actually mounted on the FPGA, resources are consumed to redirect to realtime. Currently there are no access to this resource on the FPGA for developers, only from the Realtime.

I would like some I/O Nodes for interacting with these devices on the FPGA. NI could put up some examples how they could be used.

Today the resources are invisible to the developer, except for the additional long compile time and resources used (about 7%).

I attached pictures of the FPGA design and the resources consumed for a blank vi.

Sincerly,

Jens Eriksen

[JHE]

Here are the missing pictures:

[JCC_(SK)]

Does it means when you do not need the serial and/or ethernet port then it is added to compilation anyway?

[JHE]

that is how it works today.

[Manigreatus]

I would like to have an option to remove these from the compilation, if someone is not using these ports.

[nturley]

On our Zynq-based sbRIO's, we support adding and removing peripherals from the FPGA fabric through the sbRIO CLIP Generator. You can also edit the CLIP VHDL to reroute the peripherals wherever you like, so you can drive the serial lines into the host or drive the serial lines to the outside world. So you have a lot of flexibility to do all sorts of creative things there.

I wasn't aware the peripherals consumed a significant amount of logic. The ethernet is mostly in the PS, the FPGA logic just converts the protocol. The serial ports are pretty much completely implemented in the FPGA but my understanding is that they are relatively small compared to the DMA engine we implement, but I haven't look into it too closely so I could be wrong.

Accessing peripherals from LV FPGA would be really neat, you could use the FPGA to fire ethernet packets at deterministic times. A while ago I was talking to someone about implementing an arbitration mechanism for peripheral lines. In addition to the FPGA communicating with the outside world through the peripheral lines, the FPGA could also send messages to the host through the peripherals which would be neat. Probably a lot slower and harder to use than a FIFO but still neat.