On FPGA targets, arrays get stored in BRAMs, registers, or LUTs. Since the compiler needs to allocate actual hardware resources on the FPGA, all arrays on a LabVIEW FPGA block diagram need to resolve to fixed sizes at the compile time. In order to enable creation of reusable algorithm VIs, FPGA IP Builder delays size-checking and enables you to use variable-size arrays as long as the actual size can be inferred or resolved during compilation. This example shows how to create reusable algorithm VIs by using resolvable variable-sized arrays.
FIR filters are commonly used in signal processing applications. The output of the FIR filter is governed by the number and value of coefficients supplied to it. Consider the block diagram of an 3rd order FIR filter implemented in LabVIEW below. The order of the FIR filter is governed by two elements:
1. The array of coefficients
2. The feedback node for saving state data
For a filter of order N, N+1 coefficients need to be specified.
You can implement a filter of a different order simply by changing these two elements as shown below.
The basic logic of the filter stays the same but the number of coefficients and saved state elements vary based on what order you choose to implement. Using IP Builder, you can implement both filters using a variable size FIR filter core shown in the VI snippet below.
You can encapsulate this core in a SubVI and use it in your top level IP Builder VI. Note here that, the arrays (if any) in the top level diagram will still need to have fixed sizes.
If your top level algorithm VI contains multiple instances of the core algorithm VI, the block diagram component tree contains multiple instances of the core algorithm VI. Each instance allocates its own fixed size arrays as shown in the figure below