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Using Generated FPGA IP Outside Single-Cycle Timed Loops

VIs generated by LabVIEW FPGA IP Builder can only be used in Single-Cycle Timed Loops (SCTL). However, because of other elements of your design, sometimes your application has to stay outside the SCTL. This example shows how to use a VI generated by FPGA IP Builder with logic outside the SCTL.

Consider the IP Builder generated VI shown below. x and y are scalar input and output respectively. As usual, the generated VI has handshaking signals - input valid, output valid and feedback signals.

Since the IP Builder generated VI can only be used within an SCTL, you can create wrapper loop for it as shown below

Wrapper Loop.png

This wrapper loop executes one run of your algorithm VI. One run of your algorithm VI can take multiple iterations of the loop if the generated IP is multicycle. You can now encapsulate this wrapper loop inside a SubVI and use it in your top level FPGA VI. You can wire out the loop iteration count to get an idea of the latency of the wrapped VI. Note that when you have wired outputs from the SCTL, it is important to stop the loop to obtain an output.

Now, if your algorithm has array inputs and outputs configured as Element-by-element interfaces, you can use FIFOs to exchange data with logic outside the SCTL as shown below.

Wrapper Loop_FIFOs.png

Note that Element-by-element interfaces let you provide your array inputs one element at a time. However, all elements of your input array need to be received before your algorithm can output valid data.                                                                                                                                                                                                               

If you only use FIFOs to exchange data with the rest of your application, you might not be required to stop the loop. However, if you have a mix of FIFOs and wired outputs as shown below, you will need to create a stop condition to obtain any data from the wired outputs.

Wrapper Loop_Mixed.png

If you have generated VIs with a mix of Element-by-element and Data interfaces, you must test the output patterns to decide how to stop the SCTL.   For example, if all the elements of the Element-by-element output are sent to the FIFO write node before output valid is TRUE, you can wire output valid directly to Stop, as shown in the figure above. However, if some elements are written to the FIFO write node after output valid is TRUE, you need additional logic to count the number of valid output elements from the Element-by-element interface. You can then compare the count to the number of elements expected from your algorithm to decide when to stop the SCTL.

Having a mix of interface types can complicate the creation of stop conditions for the wrapper loop. If you use mixed interface types, you should accurately characterize the output patterns of your generated VIs to prevent unexpected behavior.


Senior Product Manager
National Instruments
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