04-20-2011 04:56 PM
Hello All,
When the LM3S8962 is the master, what pin is used when chip
select is the default (0), or another value ?
Despite this question being asked a few ways in the forums,
NI's "ARM SPI Create Configuration Reference.vi" documentation
for chip select is unclear.
TI's manual is no help for NI's implementation of chip select.
NI's help for the above subvi seems not only too generic (perhaps
written for the SDK ?), but erroneous in that it reads:
"chip select specifies the chip select line to assert during the
SPI transfer. The chip select line must connect to the EEPROM
on the microcontroller. Refer to the documentation for the SPI
device for information about chip select lines."
This is useless as the ARM microcontroller has no EEPROM and
the SPI slave device documentation only covers its own pins.
The hope is to have more than one slave on the LM3S8962's single SPI bus,
without chewing up a additional pin using elemental I/O like the splendid forum
examples for ADC's and DAC's. This would save diagram real estate compared
with two sequence frames that are typically shown toggling a elemental I/O digital
output before and after writing and/or reading from the slave. It also would clarify
what on chip resource trade offs there are for each chip select number chosen.
(as most pins have multiple possible functions)
Thanks in advance for any light on this. Please don't post info on other processors
to this thread as this taints future searches on this issue with this tier 1 target.
Best,
Davy
04-22-2011 05:24 PM
Hi Davy,
While doing research on this question, I was informed that you have been working with a colleague of mine, Joel, via email for this same question. So that we do not have multiple engineers working on the same issue, Joel will be your point of contact for this issue. I ask that when you have come to a resolution, that you post that resolution here so that other customers can reference this information.
Thanks!
Aaron P
National Instruments
Applications Engineer