My FPGA module support compilation (for a locally developed module) reports a timing violation using the cRIO-9035 at any but the base clock of 40 MHz speed. I have no trouble compiling this same module with either a 9074 or 9082 with at least 120 MHz. The underlying MDK code simply takes some of the FPGA DIO lines and maps them to names we are familiar with here (EL for Event Link and RTDL for Real-Time Data Link, see attachment). The reported times for the violation don’t make any sense to me. I can instead use a 9401 DIO module in the application instance and compile just fine with it. Perhaps I’m doing something wrong with my use of the MDK, but it has been working just fine with all other targets until now. We are using LV2014 SP1. The name of our locally developed hardware and its MDK module name are "SNS-2014". Attached is a screen shot showing some of the MDK implementation and the timing error output. Thanks for any help. I submitted a trouble report (7463491), but was advised to post here for a solution. Richard.
Did you follow these steps, as seen in the white paper above and email firstname.lastname@example.org?
If you have an existing alias or have already created one email email@example.com with your direct email address and the NI forum alias name. Our goal is to update the NI web systems within 48 hours. Please check back after that time to view the forum. If you do not see the new forum once you log-in to ni.com after this time, please email firstname.lastname@example.org.
I would also include which version of the MDK module you're using.
Daniel Parrott Software Product Marketing - Data Management & LabVIEW National Instruments