But , in case I accomodate the 'Get Time.VI' in the location specified above then I would have to create an indicator to get the output of 'Get Time.VI' later use a local variable to read this value.
I think this would work. I'm not sure how deep the pipeline is on the IO read so it is possible you will get one element ahead in the time stamp. In that case you would need to use a FIFO instead of simply using a local variable. I think the documentation should show this but you could also try it and see. The other option (perhaps more elegant) is to actually control the sampling using the Get Time.VI (poll until you see >= the desired value, then sample in the next frame). Then in the "read" loop you would not need to pass the value via a local variable/FIFO because you know what time is was sampled ahead of time.
In the third While loop at the bottom in this snapshot In the False part of the Case Label Use Two DMA Writes one corresponding to the acquired Sample value(As shown in Capture.png) and the second DMA Write corresponding to the output of 'Get Time.VI' and use a Local Variable to read the updated value and write it to the second DMA Write.
Trying to use 2 DMA channels to pas the data to RT will work but will create the risk that you get out of synch pulling data from the 2 DMA channels on RT. Instead I would look into creating a cluster that contains both the sampled data and the sample time. Then pass this cluster to RT. It is easy to keep the data in synch on the FPGA and this way you eliminate the risk of getting out of synch pulling from the 2 DMA channels on RT.
After further thought, you could also look into how the waveform API does this with a T0, DeltaT, and then the data array. This would work if you are controlling the sampling from the Get Time.VI (instead of just time stamping). You would only need to pass the T0 and DeltaT once (could even pass through a front panel item). Then you don't need to try to manipulate the cluster on RT and will probably get better performance.
Thanks a lot.
I am able to understand things now. I will try the modifications you suggested and get back to you by tomorrow.
Could you please elaborate on the T0, DeltaT approach. I have read about this in few forums and would like to know more about it. Could you please share any implementations/examples using this approach.
Thanks once again.
There is good material talking about the LabVIEW Waveform Data Type. You could take the same approach. This will explain the basics:
Thanks a lot for sharing this link.
I will have a look ,get back to you and share my progress by tomorrow.
Once again thanks for all the help
I apologize for the late response.
I have tried implementing the code with a few modifications yesterday. However, I was unable to carry out the interfacing successfully.
Please find below the results of the implementation
1:I tried to create a cluster of sample value and time stamp having data type of unsigned 16 bit and unsigned 32 bit respectively. When I tried to bundle them and wite to the DMA FIFO . I was unable to wire them because of data type mismatch . As the DMA was of Fixed point data type. I have attached this in snapshot (Building_cluster_error)
2:I later used two seperate DMA Writes for a single DMA FIFO. In this case I passed the sample value to one of them and the time stamp to the other DMA FIFO. This time I was successfully able to wire them. But I think I was unable to get it right on the host VI. However, I am not too sure if this approach is correct on the FPGA side either. I am getting Timed Out on the host Front Panel and the Host VI stops suddenly.I have attached (New_modification) and (HostVI) corresponding to FPGA and Host VI respectively.
I think I am missing something important in my application.
Your further inputs would be really helpful as I am new to Labview FPGA.
I forgot to mention that I have even tried to use a while loop and placed the DMA Write within it and then used indexing to write the Sample Value and the Timestamp. However, these led to the VI being stopped with the Overwrite LED being lit up on the FPGA VI.
Could you please suggest any modifications which would take into consideration these timing constraints and allow me to accomodate the Timekeeper VI with the Acquisition VI.