In my application I am using NI cRIO 9030 for data acquisition at 1 MS/sec and using NI 9467 for GPS timestamping.
I am using 'User Controlled I/O Sampling' VI from the Labview 2014 examples section to attain maximum sampling rate of 1 MS/sec.
I need to time stamp the signal in microseconds resolution am using a NI Time Sync FPGA Timekeeper VI for this . However, I need urgent help to understand the archtecture for synchronization using NI Time Sync FPGA Timekeeper VI.
I am attaching the code I tried to implement this.
I am new to Labview FPGA and need help.
Both the acquisition and FPGA Timekeeper VI are placed on the same FPGA VI block diagram. The second VI is not the complete User Controlled IO Sampling VI but a portion consisting of the DMA Write.I checked the discussion forums . However, could not find a hint in any one of those.
It would be helpful if anyone could provide the basic interfacing of NI Time Sync FPGA Timekeeper VI for timestamping . I am able to acquire successfully at 1 MS/sec. The issue is timestamping. I have checked the Metronome VI used in the examples . However, it wont work as I am using 'User Controlled I/O Sampling'. A simple usage of timekeeper VI would help me integrate it with acquisition VI.
I don't have LV open right now but I'll try to describe the interface and usage. The timekeeper VIs (capture1.png) is running a time servo loop. The
is reading the current time from the loop. The basic operation is:
Wait on GPS PPS (digital edge)
When you get the PPS read the current time from the servo
Wait until you get the actual time of the digital edge.
Send the time the servo though and the time the GPS module provided into the servo loop.
The servo will use this information to steer the clock and keep it aligned.
If you want to use the time anywhere else in your diagram you can use the
to get the current time.
Not sure if you are trying to control your sampling rate or if you want to time stamp the acquisition. Either way you can use this VI. If you want to timestamp simply call it at the same time you tell the module to sample. If you want to control the sampling you would need to poll this VI and then when you hit you interval tell your module to sample.
Hope this helps.
- edit- images did not paste. I was trying to show the image of the time keeper VI with the "12:52" on the icon.
Thanks a lot for your prompt response.
If possible could you please insert image. It would then be much more clearer to understand.
I will briefly describe my application.
1:I am acquiring signal at 1 MS/sec.I am using NI 9223 for data acquisition and need to use 'User Controlled I/O Sampling' for data acquisition.
2:I am using NI 9467 for data acquisition. The 'NI Time Sync FPGA Timekeeper' is used for GPS Timestamping.
I am not sure how to interface the 'NI Time Sync FPGA Timekeeper' VI with the acquisition(User Controlled I/O Sampling VI).
I apologize for the VI not being clear , its because the cRIO is not currently connected.I am attaching my acquisition VI for your reference.The acquisition VI makes use of DMA FIFO.
In my 'Capture.png' file I have attempted to make few modfications to the acquisition VI.
Having kept my acquisition VI and the Time stamping VI run on the same FPGA block diagram . I attempted to make the following changes.
1:Introduced a Sequence Structure ('Capture.png') before the DMA Write in my first frame of the sequence structure used the I/O Write(I guess) and later in the second frame made use of the 'Get Time.VI' from the 'NI Time Sync FPGA Timekeeper' later I need to pass both the outputs of the sequence structure to the DMA Write through the Shift register. I am not quite sure if this is the right approach and am also not sure how do I exactly dump the data into my FIFO as the time stamp is an unsigned 64 bit value and my data samples are unsigned 32 bits.
2: On the host side I have a cRIO and use FIFO Read for acquiring the data . I need to seperate the acquired samples and the Timestamp value corresponding to each sample vaue and later display it on a spread sheet or any data log file.
I don't have LV on this machine so I can't look at your code. From the capture.png it looks like you are time stamping when the data comes back to the diagram. This will get you close but if you want to be more accurate you actually want to be time stamping when you call the convert "clock node". The read node is not the time it was sampled, it is simply when the data gets to the diagram after the pipeline.
Here is a KB with more info. Look at the second image:
You could modify the code in the KB so in the top loop you could either time-stamp using the timkeeper node in the last sequence frame or you could choose to control the loop rate by polling the time keeper in the first sequence frame.
The way you are passing the data via a pipelined FIFO looks fine. However if you want the data to be available along with the specific time stamp on RT you will need to link (bundle) the two items. There are multiple ways you could do this but you will probably want to link them on the FPGA and then pass the two to the host together. (Could use a second loop on the FPGA that reads two FIFO, bundles, and then writes to the host FIFO; perhaps can move everything into one loop and then simply bundle togther on diagram - I can't remember the timing constraints of the user controlled sampling.)
Thanks a lot for the reply.
I am attaching the User Controlled I/O Sampling VI snapshot.
I will try the implementation you suggested with the following changes
1:Add the 'Get Time.VI' in the last frame of the first Sequence Structure in this attachment below.
2:Keep the Timekeeper VI (Capture_1.png) and this VI on the same FPGA VI block diagram.
But , in case I accomodate the 'Get Time.VI' in the location specified above then I would have to create an indicator to get the output of 'Get Time.VI' later use a local variable to read this value.
In the third While loop at the bottom in this snapshot In the False part of the Case Label Use Two DMA Writes one corresponding to the acquired Sample value(As shown in Capture.png) and the second DMA Write corresponding to the output of 'Get Time.VI' and use a Local Variable to read the updated value and write it to the second DMA Write.
Could you please suggest if my understanding is correct?
I am attaching all my previous snapshots as well as the 'User Controlled I/O Sampling VI' for your reference.