* I`m using my PC as the "HOST", and FPGA as the target.
* I need to upload from the PC a binay file (~5 Kbytes) info to the FPGA memory (or maby the Real-Time target CPU?) every 30min (or even once), and start transmit it (through D/A) again and again.
* Till now, I use the FIFO MEMORY for pathing memory bytes between PC to FPGA. But in this , I have to path it once, and running it over and over in the FPGA.
* I tired to use "BLOCK-MEMORY", but the compiler is giving me this message:
Regenerating IP...
occurred during initialization of V
java.lang.Error: java.io.UnsupportedEncodingException: Cp125
ERROR:coreutil:424 - An error occurred while running Java. Please examine the
console or coregen log file for a specific IP related error.
For more information please search the Xilinx Answers Database for this
error: http://www.xilinx.com/supportFinished Regenerating.
ERROR:sim:57 - Error found during generation"circling
Shay
