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Labview FPGA compile server

Hi chikenene,

 

The answer to this question really depends on how you want this code to function. If your intention is to just run that section of code once whenever the subVI is called (not to infinitely loop), then add a control/constant to the Condition Terminal of the loop and move the indicator to the outside of the loop like you first had. 

 

You may want to take a look at the SCTL sections of the LabVIEW High-Performance FPGA Developer's Guide, or other similar training resources, to get a better understanding of what limitations there are when using these.

 

David C
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Message 11 of 14
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Dear David,

 

If I take the indicator outside the loop, the compiler uses no DSP.

Here I am stuck!

 

Evita

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Message 12 of 14
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It works on my end (see attached pics). Again, you need to architect the code in a way that makes sense. Otherwise, LabVIEW may optimize out any inconsistencies. If you still don't understand the SCTL functionality, I suggest going through the tuturials/training again to brush up on the concepts. 

 

2016-01-20_101542.png

2016-01-20_101613.png

 

David C
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Message 13 of 14
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Hi David,

 

yesterday I also tested this approach and it works.

Thank you for your help!

 

 

Evita

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Message 14 of 14
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