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Using NI 9467 GPS module

Hi

few notes:

  • I am using only one FPGA->RT DMA FIFO to transport timestamps and AIs to RT. Order of items (timestamps subparts and AI values) will never change from this reason you could trust to it and you don't need mechanism for synchronization of items in FIFO change.
  • Timestamp is spitted to 2 x 24bits and 16 bits array but after that all three arrays are converted to FXP +/-24,5 each one. That mean 16 bit subpart is expanded to 24 bits (where only 16 bits are used).
  • you could use 24-16=8bit in 3rd timestamp subpart wot carry information from GPS module as GPS is locked and GPS vs GMT offset information to RT and log it later
  • Reconstruction data on RT. Question is do you need to do it there? You could stream data to external PC only and you will reconstruct timestamps data and display data only on external networked PC.  Have you got Monitor connected to RT?
  • I would use one DMA FIFO, set-up DMA buffer size on RT to big enough (something like in example code shipped with 9223).
  • I don't know your requirements, but I expect that on RT you should have got few loops which will process data and send it to next loop.: One loop read data from DMA and send it to Processing loop which will split data to timestamp and AIs. From there you could send it to next loop which will do Publishing (for latest/actual sample by Shared Variables and by Network Stream with big buffer sizes on RT and PC side publish data for PC. When you need to backup data to RT flash (you have got only few GBs there) then you will need one more loop and when you need to display it on RT then I recommend to use one more loop with low priority (I thing you could use same Shared Variable for this) some reading
  • Display live data on PC monitor. PC monitor is not osciloscope and human will watch it => 1st) you don't have to update waveform faster then 10x second (and I would do it less), 2nd) 1MS/s when you are going to display plot with 1 Msamples on time axis - you don't have got monitor with this height resolution = undersample it.
  • Interleaving DMA to 7 arrays (3timestamps subparts + 4AI - I expect that you are using all 4 AIs). Wire first 3 array to one For Loop and reconstruct U64 timestamp, when you want you could convert it to LabVIEW (but this need 128bits in memory) then U64 array will go parallel with 4xAIs.
  • Your AI module resolution is only 16 bits. When you requirements allow it to you then you could convert AIs values from +/-24,5 to +/-16,5 FXP. Then you will lost some resolution but you will gain space on FPGA and less data will be sent to RT
  • Good test to test FPGA acquisition it to take another GPS module which generate TTL PPS and connect this PPS to your AI. Then your AI waveform will have got shape of PPS signal and your GPS timestamp should correspond to this.
  • RT to Host PC communication use Shared variables for start/stop acqusition, status of GPS, status of acq and similar (another control while loop for this).
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Message 21 of 33
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Hi,

Thanks a lot for your response and also the detailed explanation.

The link you shared was very useful as I now realize that indeed need to use network streams. My applications requirement is basically a continous data logging which should carry on for long periods of time(say hours together) and I realize that on the cRIO there is not enough memory space to support my application. Hence, I need to use network streams to transport the data along with the time stamp.

1:I realize that it would be extremely useful to dump the data values as well as their corresponding timestamps on a single DMA FIFO as that would cause no issue of synchronization on the host. However, I am a bit confused because it seems on the FPGA VI I was able to locate two FIFO's a FIFO named 'GPS Time' on the first While loop and a FIFO named 'FIFO' on the third while loop of the data acquisition loop. Could you please help me clear my understanding here.

2:Regarding the data logging process . I have the cRIO connected to my host PC using an Ethernet cross cable and I wish to transfer data using this interface . The VI used on the cRIO is the same one which was mentioned in the 'NI 9223 User Controlled I/O Sampling' Host VI.

3:I am acquiring the signal using only one channel AI0 and I do not need the remaining channels for my application.

I am new to labview FPGA and have never used these data streaming approaches in the past. I would definetly access the resources you suggested as I would like to learn more about it. However, currently I need to wind up this aspect of the application on a priority basis due to a stringent deadline. I would be really grateful if you could provide me with certain architecture, if available which could support my current application.

Once again thanks a lot for the help.

Regards.

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Message 22 of 33
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Hi

your points:

  1. on FPGA code I have got one DMA FIFO which send 3+4 FXP values to RT. Second 'GPS Time' FIFO is local FPGA FIFO to send timestamp from while loop where I/O pulse was generated to while loop where you are reading values from AI module. Because this two while loops and you don't want to lose any timestamp (in theory on FPGA this should not happed because you could calculate/count how many tick you need for everything) size of this 2nd FIFO set-up for 3 elements. And FIFO implementation is set-up as 'flip-flops'
  2. RT implementation. As I mentioned in my previous respond. You will need few while loops on RT to do Acquisition (extract values (DMA FIFO)) from FPGA, to display actual values for host PC and to stream everything to host PC. Because your PC is connected directly then you have to only stream data to PC and do all this display last values only there.
  3. When you are using only one AI then number of values in one sample from your FPGA will be 3+1 FXP. After this modification your compilation time will be shorter. In teory your FPGA -> RT FIFO could be U64 type with two elements (one for timestamp and one for 24,5 FXP converted to U64 bits, then on RT you will convert it back to FXP or you could do it on your host PC)

Ofcourse good thing is NI's Real-Time course 1 and 2 and FPGA. But it look like you dont have got time for this.

More reading NI LabVIEW for CompactRIO Developer's Guide

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Message 23 of 33
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Hi ,

Thanks a lot for your input.

I am now able to understand the FIFO implementation on the FPGA side.

What I observed in my current case is that once I start to log the values onto the cRIO continously I get an error stating the cRIO memory utilization has exceeded.Post that once again if I run the VI the host VI simply does not run and it stops immediately , while the FPGA VI is still running. Considering , the following issues while acquiring data continously I believe network streaming would be the best option to suit my needs for continous data logging.

I am indeed short of time I would definetly like to go through the labview FPGA course , however currently I really need to keep pace with the acquisition and timestamping process as I have spent lot of time on it but I could not get the required results, also I am a novice to the synchronization techniques this makes it bit trickier to wrap up this part of the application.

I will definetly have a look at the cRIO developer guide for the Network Streaming,It would be nice if I could get an example of network streaming which probably would suit this kind of application, or if Network Streaming was used for such kind of situation, as it would clear my understanding in this limited span of time.

Thanks.

Regards.

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Message 24 of 33
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Hi

you have to find out why your RT code stop.

Few hints how to debug your RT:

  • create indicator from i terminal in while loop (reading DMA FIFO)- then you will know how many times your while loop run
  • do not display timestamps and AI values on front panel and not in waveform indicator - this will load CPU very much. Display only firt idemt from arrays when you want to see something
  • add parallel while loop which will read RT CPU load and memory load (10 per sec)
  • when you have got error find out which block generate error

I don't have got examples of network streams - you should find some in examples or on web.

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Message 25 of 33
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Hi,

Thanks a lot for your response.

I will try to trouble shoot the issue with the steps you suggested and get back to you.

Could you also please confirm the configuration of the DMA FIFO named as 'FIFO' in the FPGA VI configuration which you suggested?

Thanks.

Regards.

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Message 26 of 33
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Hi

FPGA code is from example code shipped with LabVIEW and there they called DMA FIFO (FPGA to RT FIFO) 'FIFO'.

When you are modifying RT code, then property node/invoke method connected to FPGA reference wire will 'pharse' FPGA code and will find all FIFOs accessible from RT. (You could rename it to something better).

PS: In another thread you had question about datatypes of DMA FIFO. Answer is that only standard numeric datatypes are supported between RT and FPGA. You can not use custom datatype and/or clusters - unfortunately. You could vote fot this idea here.

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Message 27 of 33
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Hi,

Thanks a lot for your prompt response.

I just wanted to know the confguration of the FPGA to RT DMA FIFO which was used in the Labview FPGA VI you mentioned , in terms of the data type because what I figured out today was that I guess I am unable to write both the time stamp and the sample values onto the same FPGA to RT DMA FIFO and the reason which causes the host VI to stop is that there are no elements written to the DMA FIFO . Hence, it causes an error after the FIFO READ and the stop and the Error flag go high which causes the VI to stop.

I guess the issue lies in the data type of the FPGA to RT DMA FIFO. I am unable to use Build Array properly to append both the Time stamp and the sample values.The sample values are of Fixed point and the Unsigned 64 bit timestamp is split into 24, 24 and 16 bits of Fixed Point data type,as suggested. However, I am still unable to write them onto the FPGA to RT DMA FIFO.

Could you please suggest.

Thanks.

Regards

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Message 28 of 33
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Hi,

I tried to understand certain concepts of Labview FPGA and also like to summarize my understanding

In the Labview FPGA code for time stamping there are the following considerations

1: The datatype for the local DMA FIFO would be Fixed Point with 24,5(by this I interpret the total bits to be 24 and the bits in the integer part to be 5)

2:The total number of elements are configured to 3

3:The data type of the FPGA to RT DMA FIFO would be Fixed Point with 64,5 (by this I interpret the total bits to be 64 and the bits in the integer part to be 5)

4:The total number of elements in this case would be set to two , the first one corresponding to the 64 bit timestamp and the second corresponding to +-24,5 FXP sample values.

5:The unsigned 64 bit FXP value is split into 24,24 and 16 bits which is packed into an array using build array and written into the FPGA to RT DMA FIFO and the second set refers to +-24,5 FXP sample values.

6:The +-24,5 FXP sample values are converted into 64 bit unsigned integer as well as the build array corresponding to the timestamp is converted into unsigned 64 and fed to the DMA Write.

I have read in an article that the DMA transfer uses 32 bits so data conversion into 64 bit before writing into the FPGA to RT DMA FIFO would it cause data transfer issues.

I checked that the use of DMA Write inside the For loop causes the same values to be repeated indefinetly and new values are not witten so would this approach work?

Thanks.

Regards.

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Message 29 of 33
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Useful writing - I learned a lot from the information - Does someone know if I would be able to get a sample a form form to fill out ?

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Message 30 of 33
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