Thanks a lot for your response and also the detailed explanation.
The link you shared was very useful as I now realize that indeed need to use network streams. My applications requirement is basically a continous data logging which should carry on for long periods of time(say hours together) and I realize that on the cRIO there is not enough memory space to support my application. Hence, I need to use network streams to transport the data along with the time stamp.
1:I realize that it would be extremely useful to dump the data values as well as their corresponding timestamps on a single DMA FIFO as that would cause no issue of synchronization on the host. However, I am a bit confused because it seems on the FPGA VI I was able to locate two FIFO's a FIFO named 'GPS Time' on the first While loop and a FIFO named 'FIFO' on the third while loop of the data acquisition loop. Could you please help me clear my understanding here.
2:Regarding the data logging process . I have the cRIO connected to my host PC using an Ethernet cross cable and I wish to transfer data using this interface . The VI used on the cRIO is the same one which was mentioned in the 'NI 9223 User Controlled I/O Sampling' Host VI.
3:I am acquiring the signal using only one channel AI0 and I do not need the remaining channels for my application.
I am new to labview FPGA and have never used these data streaming approaches in the past. I would definetly access the resources you suggested as I would like to learn more about it. However, currently I need to wind up this aspect of the application on a priority basis due to a stringent deadline. I would be really grateful if you could provide me with certain architecture, if available which could support my current application.
Once again thanks a lot for the help.
Ofcourse good thing is NI's Real-Time course 1 and 2 and FPGA. But it look like you dont have got time for this.
More reading NI LabVIEW for CompactRIO Developer's Guide
Thanks a lot for your input.
I am now able to understand the FIFO implementation on the FPGA side.
What I observed in my current case is that once I start to log the values onto the cRIO continously I get an error stating the cRIO memory utilization has exceeded.Post that once again if I run the VI the host VI simply does not run and it stops immediately , while the FPGA VI is still running. Considering , the following issues while acquiring data continously I believe network streaming would be the best option to suit my needs for continous data logging.
I am indeed short of time I would definetly like to go through the labview FPGA course , however currently I really need to keep pace with the acquisition and timestamping process as I have spent lot of time on it but I could not get the required results, also I am a novice to the synchronization techniques this makes it bit trickier to wrap up this part of the application.
I will definetly have a look at the cRIO developer guide for the Network Streaming,It would be nice if I could get an example of network streaming which probably would suit this kind of application, or if Network Streaming was used for such kind of situation, as it would clear my understanding in this limited span of time.
you have to find out why your RT code stop.
Few hints how to debug your RT:
I don't have got examples of network streams - you should find some in examples or on web.
Thanks a lot for your response.
I will try to trouble shoot the issue with the steps you suggested and get back to you.
Could you also please confirm the configuration of the DMA FIFO named as 'FIFO' in the FPGA VI configuration which you suggested?
FPGA code is from example code shipped with LabVIEW and there they called DMA FIFO (FPGA to RT FIFO) 'FIFO'.
When you are modifying RT code, then property node/invoke method connected to FPGA reference wire will 'pharse' FPGA code and will find all FIFOs accessible from RT. (You could rename it to something better).
PS: In another thread you had question about datatypes of DMA FIFO. Answer is that only standard numeric datatypes are supported between RT and FPGA. You can not use custom datatype and/or clusters - unfortunately. You could vote fot this idea here.
Thanks a lot for your prompt response.
I just wanted to know the confguration of the FPGA to RT DMA FIFO which was used in the Labview FPGA VI you mentioned , in terms of the data type because what I figured out today was that I guess I am unable to write both the time stamp and the sample values onto the same FPGA to RT DMA FIFO and the reason which causes the host VI to stop is that there are no elements written to the DMA FIFO . Hence, it causes an error after the FIFO READ and the stop and the Error flag go high which causes the VI to stop.
I guess the issue lies in the data type of the FPGA to RT DMA FIFO. I am unable to use Build Array properly to append both the Time stamp and the sample values.The sample values are of Fixed point and the Unsigned 64 bit timestamp is split into 24, 24 and 16 bits of Fixed Point data type,as suggested. However, I am still unable to write them onto the FPGA to RT DMA FIFO.
Could you please suggest.
I tried to understand certain concepts of Labview FPGA and also like to summarize my understanding
In the Labview FPGA code for time stamping there are the following considerations
1: The datatype for the local DMA FIFO would be Fixed Point with 24,5(by this I interpret the total bits to be 24 and the bits in the integer part to be 5)
2:The total number of elements are configured to 3
3:The data type of the FPGA to RT DMA FIFO would be Fixed Point with 64,5 (by this I interpret the total bits to be 64 and the bits in the integer part to be 5)
4:The total number of elements in this case would be set to two , the first one corresponding to the 64 bit timestamp and the second corresponding to +-24,5 FXP sample values.
5:The unsigned 64 bit FXP value is split into 24,24 and 16 bits which is packed into an array using build array and written into the FPGA to RT DMA FIFO and the second set refers to +-24,5 FXP sample values.
6:The +-24,5 FXP sample values are converted into 64 bit unsigned integer as well as the build array corresponding to the timestamp is converted into unsigned 64 and fed to the DMA Write.
I have read in an article that the DMA transfer uses 32 bits so data conversion into 64 bit before writing into the FPGA to RT DMA FIFO would it cause data transfer issues.
I checked that the use of DMA Write inside the For loop causes the same values to be repeated indefinetly and new values are not witten so would this approach work?
Useful writing - I learned a lot from the information - Does someone know if I would be able to get a sample a form form to fill out ?