Using NI 9223 the signal is acquired at 1 MS/sec. However, there is a limitation on the number of samples we can acquire using the User controlled I/O sampling as the FPGA VI times out.Could you please suggest an alternative approach to continously acquire the signal at 1 MS/sec without timing out I tried to increase the FIFO buffer size . However, it seems the labview does not work properly.
Any other alternative , if anyone could please help!!