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Acquire data continously at 1 MS/sec using cRIO 9030 and NI 9223 controller

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Hi,

I am facing another issue with the basic acquisition  I am using cRIO 9030 controller and NI 9223 . It seems the User controlled I/O sampling does sample at 1 MS/sec . However, it does not acquire data continously and gets timed out frequently. I have referred to a similar post

http://forums.ni.com/t5/Real-Time-Measurement-and/NI-9223-at-1Mhz-on-a-cRIO-9024/td-p/2892950/page/2

However, my application does not require me to plot a graph so can this reduce additional overhead of the host and allow me to acquire the signal at 1 MS/sec continously and log the data on the crio.If I use the 'Producer' 'Consumer' architecture.

Could you also please suggest if there is any other architecture to accomodate this.

Thanks.

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I am referring to the User Controlled I/O sampling example found in the examples of Labview 2014

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Hi,

I also had a question if increasing the size of DMA FIFO would actually help I plan to continously acquire the data for say half an hour . I had tried this earlier but it seems the Labview freezes. If this seems to be the solution can anyone please explain the maximum limit for the size of a DMA FIFO and how to increase the size of DMA FIFO on the host as well as the FPGA. I think the FIFO on the FPGA is visible on the project window.

Please help me!

Regards.

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Hi Harss,

Have you checked your code for memory leaks?  Is there any regularity to how many samples are captured before LV times out?  What is the source of the timeout?  Can you post your code so it can be examined?

C

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Hi,

Thanks a lot for your prompt response.

Please find my answers to your question below

1: I am not quite sure about the number of samples acquired. However,when I plotted the signal on the graph it seemed about 19,000 odd samples which was the maximum limit of the waveform graph data points . The only modification made to the existing code in this case was that I didnt make the FPGA VI stop once the acquired samples were greater than the number of samples specified on the front panel

2:The FPGA VI gets timed out and I can see the Time out LED glow on the front panel on the FPGA VI. I tried to increase the Depth of the FIFO on the host VI however was not able to stop the FPGA VI from being timed out.

I will send you the snapshot of the code ASAP.

Thanks once again

Regards.

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Hi Harss,

I cannot look at your code because the newest LV version I have is 2014.  I thought that your application did not require you to plot the graph.  Graphs can be a source of problems, if you have one in your application, try getting rid of it.  Does the relation between 19,000 odd samples being the max the graph can take and that being where you time out provide any hints? Your entire application consists of only two VIs?  That seems a little odd but then again, I wasn't able to open it.  Feel free to include the VIs as a screenshot if you can't save as a 2014 VI.

Could it be that your FPGA VI is buffering as much as it can and your host is not unloading it as fast as it needs to and so your FPGA side gets full?  Can you add some code to track how many sets of data are in each when the timeout occurs?  That is what I think I would do in a similar situation.

Does the timeout error give any relevant information?  What is the error code?

C

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