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Timing Violation in 802.11 Framework

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Timing Violation in 802.11 Framework

Hi 

 

I have added some additional logic in Power Measurement block in the 802.11 design. The design is not compiling and give timing violations (as small as 0.16ns and as large as 2ns) at feedback nodes. I have compiled it multiple times, but it is still giving errors. The delay is in the data path.

 

The manual says "If your failed compilation misses the required throughput time by only a few nanoseconds, try recompiling your  bitfile. Each compilation of a bitfile does not always produce identical results on the FPGA, so recompiling sometimes resolves minor timing violations." 

 

My question is: How many nanoseconds is considered a 'minor timing violation'? I compile the exact same logic number of times in hopes that recompiling might resolve the timing but it didn't.

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Message 1 of 7
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Re: Timing Violation in 802.11 Framework

Hi Hira,

 

This is caused because the compiler cant guarantee that all the code that you want to run in 1 clock-cycle will be done in that time. 

 

What you can try is to compile the FPGA with Speed Optimization. (Found under build specs)

 

If this does not work you will have to lower the clock-speed in order to conform to the timing specifications.

 

Kind regards,

 Natan Biesmans

Message 2 of 7
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Re: Timing Violation in 802.11 Framework

Compiling an FPGA design is not a linear task.  Long story short, the compiler starts (seeds) at different places each time and may result in different results.  This is why they say if a minor timing violation occurs it can be resolved by recompiling since it may seed elsewhere and solve things.  If you retried then yours may not be 'minor' enough.  They cannot give a number since it is based on too many factors.

The above suggestion is good, to try different settings; note that not all FPGA targets or older versions of LabVIEW FPGA support this feature.

Can you pipeline or reduce bits (width) being processed?

When you compile this without your logic, what is the maximum timing of the loop in question (from compile results)?


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Message 3 of 7
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Re: Timing Violation in 802.11 Framework

Can you please tell me where can I find this option in Communication System Design Suite? I have check FPGA Compiler Preferences in Build Options, but couldn't find this option. 

 


@NatanBiesmans wrote:

 

 

What you can try is to compile the FPGA with Speed Optimization. (Found under build specs)

 

 

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Message 4 of 7
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Re: Timing Violation in 802.11 Framework

Hi Hira,

 

I'v appended a screenshot on where you can find the settings you are searching for.

 

build_specification.PNG

 

Als see this reference for more information about the different settings:

http://zone.ni.com/reference/en-XX/help/371599K-01/lvfpgadialog/fpga_build_spec_xilinxvivado_db/

 

Kind regards,

 

Natan Biesmans

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Re: Timing Violation in 802.11 Framework

Hi Natan 

 

I think you are using the LabVIEW FPGA Module. I am using LabVIEW Communications System Design Suite and cannot find this option. Screenshot attached. 

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Message 6 of 7
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Re: Timing Violation in 802.11 Framework

Hi Hira,

 

When I see your sidetab, can it just be that you are trying to see how fast you can run the code?
It seems that you just hit the top speed at which you can use the code.

Kind regards,
Natan Biesmans

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