A multirate file was developed and tested with success on host. The file envolves add, minus, multiplication, operations complex to polar conversion and conjugate.
When I change the target from Host to USRP appears:
- Error: the optimized FPGA VI did not compile correcly
- Warning: informing that the clock rate cannot be reached
I didn't select the option "Optimized FPGA" for any one file on this project.
The Throughput for each input and output to low value: 1 Msps
The clock rate value for the file was configurate with 4 MHz and with 40 Mhz, but the problem not disapear;
Do you have some suggestion how solve this problem?
The picture show the mentioned errors.
Thanks in advance.
Have a nice day.
