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802.11 Application framework

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Hello all,

I have started just recently to work with the 802.11 application framework with the USRP2953. Without knowing much yet about the framework I need to pose this question: Is it possible to extract the logic of the framework and run it independently from hardware,i.e. without the use of the USRP or any other hardware? 

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Accepted by topic author labviewette
09-15-2015 12:56 AM

Hi!

 

"Running" the framework in the sense of real-time execution is only possible with hardware. However, for debugging purposes and system test you can extract parts of the design (e.g. the transmitter chain or the receiver chain) and run it in simulation mode. Two options are available:

1. "Run FPGA Simulation" node: can be used to simulate Clock Driven Logic (GCDL files). One execution of this node corresponds to one FPGA clock cycle.

2. Create a new FPGA toplevel, e.g. including only the TX or RX processing loop. Now this toplevel can be simulated by using the standard "FPGA Host Interface" when configuring the "Open FPGA" node to "Simulate Build Spec". This option allows exchanging of data using Target-to-Host and Host-to-Target FIFOs simular to real FPGA execution. The only thing you have to be aware (especially when stimulating the design with input values) is that the FPGA simulation executes considerably slower than real FPGA execution.

 

Regards,

Jörg

 

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Hello Jörg,

 

In LV Communications 2.0 with Framework 802.11 FPGA USRP RIO 40 MHz BW STA i can't set Simulate mode in Open FPGA VI Reference it just closed. What is the problem

 

Please Help. Thank you. 

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You need to build your application and choose a bitfile as a build output in the Item Properties of the FPGA STA.gvi on the top level module of your application.

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It depends on your purpose. I am mainly working on MAC part, so there is no need for me to simulate the PHY functionality. So, I build a silmple "pass through" PHY, which I'm using for the simulations. If you would like to also simulate PHY functionality, it turned to me to be very-very-very slow, and also I was able to make TX PHY running, but not the RX part of it yet.

 

For simulating MAC, you still need to make some changes on the Host VI also, since it was never designed to be run in simulation mode. Here, you could create a "simulation"-Boolean by means of which you could switch on/off all the parts of the Host, which are hardware related (otherwise the simulation would just crash).

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