I'm new to labVIEW and trying to create a serial communication custom device for VeriStand, but have problems to convert data between RT FIFO read/write and VISA read/write.
Here is what I tried to implement:
"RT FIFO Read" VI gets data from input channel, the data is then written to serial port via "VISA Write" VI
"VISA Read" VI receives data from serial port, the data is then written to output channel via "RT FIFO Write" VI
Attached "dataPath.JPG" is the data path but seems not correct. Any suggestion will be very appreciated.
By the way, how to debug the RT driver of asynchronization custom device in LabVIEW? Is it independent from VeriStand?
Thank you for the help!
I tried what you said, but have problem with wiring. Would you please help to take a look?
Here is the wiring:
"Unflatten From String" with type of an array of double, its output pin "value" is connected to "new element/subarray" pin of "Replace Array Subset" (doesn't work here)
"n-dimension array" pin of "Replace Array Subset" is connected to "Dev. Outputs" line
"output array" pin of "Replace Array Subset" is connected to "element" pin of "RT FIFO Write"
All I tried to do is to convert a 1-D array of double to string for the input, and convert a string to an array of double for the output.
build a cluster and then use the typecast is what I searched online.
The wiring problem is fixed - type problem
Now there is no serial communication at all. I used "portmon" to monitor the COM port communication and it seems the port is open and then closed.
Can anyone help to take a look at the attached custom device RT driver?
Is there any way to debug the RT driver in LabVIEW? I can only find out if it is working by adding the custom device to VeriStand project and run the project, but don't know how to debug it.
Very much appreciated for any help.
I've tried again, and managed to write constant string to serial port and read it back, without using the RT FIFO.
But still have problem reading input data from VeriStand input channel via RT FIFO Read, and writing output data to VeriStand output channel via RT FIFO Write.
The attached file is the RT driver. Any suggestion will be very much appreciated.
Yes, I think it is the interface problem between VS and the RT driver. Thank you for pointing out the VS forum. I was not able to find it.