I am still having the same issue as in a previous thread. I am using a microcontroller to talk to the TNT4882. During write cycles, the microcontroller correctly sends the address, csn, wrn and data signals to the TNT and all the signals are within tolerances of the generic mode ac timing characteristics from the tnt data sheet. However, the TNT does not consistently respond with the RDY1 signal which would indicate the data had been latched. The RDY1 only seems to work correctly when I am talking to specific registers, FIFOA, FIFOB, INTR, HSSEL, ADR, and the TIMER registers, but when I address any other register, the TNT fails to respond. On a read cycle, the TNT has the tendency to work even less, the only r
egisters I have been able to read from are the FIFOA and FIFOB registers. Once again, the microcontroller correctly asserts the address, csn, rdn, and data signals while the TNT fails to respond with a RDY1 pulse. The CPUACC pin was asserted during these failed I/O cycles, however I lengthened the I/O cycle greatly (the wr and rd pulses last around 500 ns), which should easily be sufficient, however, I am still only able to communicate successfully with those specific registers. What could be preventing me from completing I/O cycles with only certain registers on the TNT?
