There appears to be conflicting information between 2 documents regarding the timing diagram details for processor-to-9914 communication for a parallel interface (read and write). I would like to know which of the 2 documents has the correct timing information to be used for correct communication to the NAT9914. The 2 documents are:
IEEE 488.2 Controller Chip, 372013B-01, Sep06
Application Note 110, Designing a GPIB Device Using the NAT9914, 341398A-0, January 1998
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I am looking further into this discrepancy. Right now, I would recommend looking at the NAT9914 IEEE 488.2 Controller Chip Specification as your reference since the application note is older and has been removed from our website.
I will post here when I have confirmed the correct timing specifications.
I used the timing specs in NAT9914 IEEE 488.2 Controller Chip Specification, and haven't had any problem communicating with the chip, so far.