Configure DMA from Target to Host in cRIO-9075

[iozana]

Hi,

I recently bought the cRIO-9075 but in order for me to design the software-firmware architecture I need to get same answers for the following questions (I'm a beginner in labVIEW FPGA):

1. In this Compact RIO (9075) I have 5 DMAs buss between the Host (Real Time controller) and the target (FPGA). The first one is set from "Host to Target- DMA" (let's call it DMA1) and the other 4 is from "Target to Host-DMA". In my Target application I have four separate parallel loops that itch of then is sending different data to the host. My question is how can I set the compiler for etch loop to use DMA2 for loop 1, DMA3 for loop 2, DMA4 for loop 3 and DMA5 for loop 4? Is it by different names? How does he know to use different DMA for etch loop? In addition, Is it possible to write and read to etch DMA at the same time (etch from different parallel loop).
2. My second question is related to the previous question, what will I do if I'll having let's say, 10 different (loop instead of 4, again, unrelated)? I only have 4 DMA's left…? Can I use 10 different names (Buffer Items) somehow to all 4 DMA's
3. I know that for same target the DMA bus is configure to transferring unsigned, 32-bit (U32). In this cRIO, I think I can configure the DMA data type to let's say U8 (for example). My question is if I configure it to U8 do I utility the bus for the maximum rate or should I packed the U8 to U16 using the Join and Split function block? What is the more efficient way to transferring date?

Thanks a lot,

Idan

[RikkiTikkiTucker]

Hi Idan!

The DMA that you are currently using is based on the name that you give it.  As for how it works and how many DMA channels you have available, I would recommend checking out this documentation:

Using DMA FIFO to Develop High-Speed Data Acquisition Applications for Reconfigurable I/O Devices

http://www.ni.com/tutorial/4534/en/

cRIO-9075 Operating Instructions

http://www.ni.com/pdf/manuals/375650b.pdf

Thanks!

[iozana]

Hi,

Thank you for your response!

I review those documents that confirmed that I Indeed have 5 DMA in the cRIO-9075. Unfortunately, I still don’t know is it possible to use let's say, 10 different DMA's names from unrelated parallel loops…  (and maybe labview will multiplex between them all…).

Thanks alot,

Idan

[crossrulz]

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iozana wrote:

I review those documents that confirmed that I Indeed have 5 DMA in the cRIO-9075. Unfortunately, I still don’t know is it possible to use let's say, 10 different DMA's names from unrelated parallel loops…  (and maybe labview will multiplex between them all…).

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You can do the multiplex youself.  I typically use a single DMA for sending commands/data to the FPGA and a second DMA for sending data to the RT/host.  You have one loop that reads the incoming DMA and use other FIFOs to send the commands/data to whoever needs it.  The key is to make the data type in the DMA a big data type (like U64 or U32) and build up you command ID and data into that.  I typically use 1 byte for the command ID (or destination ID), leaving the rest of the word for your data.  You can do the same for your return data.

So with that set up, you just need 2 DMAs.  It works extremely well for non-high speed data.  Anything really high speed should have its own DMA.

I can't remember the name of this architecture (messanger?), but if you dig through some of the NI Developer Days prensentations, you will find one about making FPGA code extendable.  This was discussed in that presentation.

[crossrulz]

I found the presentation from 2014.  There is a 2015 version floating around too, but I don't have time to search for it.  https://decibel.ni.com/content/docs/DOC-36048

So what I was attempting to describe is called the Reactor Pattern.  It is discussed at the end of the presentation.